SU801252A1 - Counter - Google Patents

Description

one

The invention relates to a pulse technique / in particular to circuits for starting, stopping and controlling a counter, and can be used in various digital circuits. Requirements for increased reliable information, as a binary or binary-decimal counter, working on addition or subtraction, as well as as a register for recording parallel or sequential information, its storage and shift, and can be used in automation and computing devices.

A counter is known, the content of t is the countable nodes, the outputs of the senior arrays of which are connected to the entrances of the majority elements, the outputs of KOtopiaoi are connected through logical inputs to the inputs of the counter ll.

The disadvantages of this counter are limited functionality and low reliability of operation.

Also known are the counters that contained the block of majority elements, the first second and third registers and the adder, the outputs of which are connected to the input. registers whose outputs are connected

with the inputs of the t2l majority elements block.

The lack of a counter is blocked by the impossibility of reversing the account in binary and decimal code.

The purpose of the invention is to provide reverse accounts in binary and real, with real codes.

The goal is achieved

0 in that the counter contains a block of majority elements, the first, second and third regasters and the sukmator, which are connected to the inputs of registers whose outputs are connected

5 with the input block W of the majority elements, the input elements AND, AND-NOT, OR, the first, second and third elements of the prohibition and nepstxR and the second commutator, the outputs of the coils are connected to the input

0 of the adder, the transfer input of which is connected to the output of the first prohibition element, the first and second control inputs of the xc4 switches are connected to the output of u «i, respectively, of the second and

5 of the third prohibition elements, the inputs of the second and third bits of the second channel of the first switch are connected to the output of the And element, the inputs of the second and third bits of the third

0 channel of the first ko is connected to the output of the NAND element, the common bus connects the inputs of all bits of the first channel of the first switch, the inputs of the first and fourth bits of the second channel of the first switch, as well as the inputs of all bits of the first and fourth channels of the second switch, The input bus of the first and fourth bits of the third channel of the first switch is connected to the power bus, the inputs of all the bits of the second and third channels of the second switch are connected to the outputs of the block of majority elements, the output of the OR element is connected to the beat by the first inputs of the registers, the first inputs of the OR element, the first, second and third prohibition elements are connected to the reset input of the counter, and the second inputs of the OR element, the first, second and third prohibition elements are connected respectively to the recording buses and the first, second and third, controllable The fourth bus is connected to the first inputs of the AND and AND-NOT elements, the remaining inputs of which are connected to the outputs of the majority elements, and the fifth, sixth and seventh control buses are connected to the first, second and third registers of the gate inputs.

The drawing shows a counter, a block diagram.

The counter contains a block of majority elements 1, first 2, second 3 and third 4 registers, cyNwaTOp 5, first prohibition element b first 7 and second 8 switches, second 9 and third 10 prohibition elements, element 11, AND-NOT element 12 and element OR 13. The outputs of the adder 5 are connected to the inputs of registers 2, 3 and 4, the outputs of which are connected to the inputs of the block of majority elements 1, the outputs of the switches 7 and 8 are connected to the inputs of the adder 5, the transfer input of which is connected to the output of the first prohibition element b first and second the control inputs of switches 7 and 8 are connected to you by the moves of the second 9 and third 10 prohibition elements, respectively, the inputs of the second and third bits of the second channel of the first switch 7 are connected to the output of the AND 11 element, the inputs of the second and third bits of the third channel of the first switch 7 are connected to the output of the AND-HE element 12 bus 14 connects the inputs of all the bits of the first channel of the first switch 7, the inputs of the first and fourth bits of the second channel of the first switch 7, as well as the inputs of all the bits of the first and fourth channels of the second switch 8 to the power bus 15 are connected The inputs of the first and fourth bits of the third channel of the first switch 7 are the inputs of all the bits of the second and third channels of the second switch 8 connected to the outputs of the block of majority elements 1, the output of the OR element 13 is connected to the clock inputs of registers 2, 3 and 4, the first inputs of the element OR 13, the first 6, the second 9 and the third 10 ele. interdiction elements are connected to the reset input 16 of the counter, and the second inputs of the OR element 13, the first 6, the second 9 and the third 10 prohibition elements are connected respectively to the recording bus 17 and the first 18, the second 19 and third 20 control buses, the fourth control bus 21 And 11 and AND-NO 12 elements are connected to the first inputs of the elements, the remaining inputs of which are connected to the outputs of the block of the majority elements 1, and 22, the pole 23, and the seventh 24 control bus are connected to the first, second, and third controllers, respectively. inputs of registers 2, 3 and 4, Quad inputs th channel of the first switch are connected with the parallel input 25 of the counter.

The mode selector is performed by applying signals to the control inputs in accordance with the table, and switching occurs via signals supplied to bus 22 when shifting the parallel code and writing the serial code.

The counter is set to the zero state by a pulse on bus 16, which blocks the signals on buses 18, 19 and 20. From the output of the prohibition 9 and 10 elements, the control inputs of the switches 7 and 8 receive signals that open the first channels, the inputs of which are connected to common bus 14. Thus, the inputs of the adder 5 arrive from three numbers: 0000 - to the input A of the adder 5 from the switch 77 0000 - to the inputs B of the adder 5 from the switch 8, O - to the transfer input cyNwaTopa 5 from the element

6 prohibition OOOO - the received amount from the output of sulmator 5 on the impulse on bus 16, coming through the element OR 13 to the inputs of registers 2, 3 and 4.

When operating as a binary addition counter, the control signals are set in accordance with the table. The signals on buses 19 and 20 open the second channels of the switches

7 and 8, After setting the counter to the 0th state at the output of the adder

5 sets a number equal to the sum of the three terms 0000 - at the inputs A of the adder 5 from the switch 7 0000 - at the inputs B of the adder 5 from the switch 8, 1 - at the transfer input of the adder 5; 0001 - this code is entered into registers 2, 3 and 4 by a clock pulse on bus 17.

On the second clock pulse on the bus 17 in the registers 2, 3 and 4 of the adder 5 will be recorded a number equal to. newly suiule three components: 0000 - at inputs 4 of adder 5 from commutator 7, 0001 - at inputs B of adder

5 from switch 8; 1 - at the input of the transfer of the adder 5j 0010 - the sum of the cows, etc.

TaKtiM, after each clock pulse, the contents of registers 2, 3 and 4 are incremented by one, which corresponds to the binary counter operation for addition.

The mode of operation of the binary-decimal addition counter differs from the operation of the decimal addition counter by the fact that the control signal on the bus 21 includes an AND 11 element, which participates in the formation of a correction code. The inputs of the logic element 11 are connected to the outputs of the 1st and 4th bits of the block of the majority elements 1. When the contents of registers 2, 3 and 4 reach the value 1001, the inputs of the adder 5 from the output of the switch 7 receive the ITO code, which is summed with the content . the registers arriving at the inputs B of the adder 5 through the second channel of the switch 8. From the outputs of the adder 5 to registers 2, 3 and 4 a clock equal to the sum of three terms is written to the registers 2, 3 and 4: ITO is the number at the inputs A of the adder 5 f correcting, 1001 - number at the inputs In the sukalyator 5 1 - at the input of the transfer of the adder 5} 1-0000 received sum.codes. The number 0000 is recorded in the registers and at transfer output 26 of the adder 5 a transfer unit is formed in the next tetrad. If the value of the number recorded in registers 2, 3 and 4 is less than 1001, then the number 0000 is fed to the inputs A of the adder and the operation of the counter to the value 1001 is similar to the operation in the binary counter mode.

When a universal redundant subtraction counter is operated in binary code, the control signals are set in accordance with the table. The signals on buses 19 and 20 open the third channels of switches 7 and 8. AND-NOT 12 is wrenched out. Assuming that registers 2, 3 and 4 contain the number 1101, then the output of adder 5 sets a number equal to the sum of three syladeks: 1111 at Outputs A of adder 5 from the first switch; 1101 - at the outputs B of the adder 5 - the number recorded in the pax 2,, 3 and 4, O - at the transfer input of the adder 5, 1-1100 code, which by the clock pulse on the bus 17 enters the registers 2, 3 and 4. The count value decreased by 1, which corresponds to the operation of the subtraction counter. A transfer unit is sent from the transfer output of the adder to the next tetrad.

When deducting binary-decimal numbers, the element-AND-NOT 12 is included,

which forms the correction code. arriving at the inputs A of the adder only when the value of the number recorded in registers 2, 3 and 4 is 0000. For example: 0000 is a number on 5 inputs B of the adder 5 - the contents of the registers 2,3 and 4/1001 are the numbers On the inputs A of the adder 5, the correction code, O, at the transfer input of the adder 5, 1001 is the content of the output Q of the adder, which is entered in registers 2, 3 and 4 on the next clock pulse on the bus 17.

If the value of the number recorded with in registers 2, 3 and 4 is not equal to 0000, then, as in the case of binary subtraction, the number 1111 arrives at the input A of adder 5 from switch 7.

Writing parallel code occurs in accordance with the table. Signals on buses 19 and 20 open the fourth channels of switches 7 and 8. Through switch 7, inputs A of adder 5 receive an input code. On

Inputs In adder 5, commutator 8 receives a code 0000. Bus 18 through | gives a logic zero level. From the output of adder 5, a pulse corresponding to the inputs-25 of the fourth channel IKOivBviyTaTopa 7 is written to the registers 2,3 and 4; if the code recorded in the registers needs to be shifted, then the shift pulses are fed to the inputs

registers 2, 3 and 4 on bus 22, and control signals are set in accordance with the table. The recording of sequential information occurs. According to the impulses arriving on

bus 22, and input information is fed to bus 24.

When the universal redundant counter is operating in both binary and binary-decimal mode

counter for addition and subtraction, in addition to the high reliability and reliability of the contents achieved by the majority reservation | at each clock pulse, the content of any of the three registers is corrected if it accidentally fails. This is achieved due to the logical feedback on the block of majority elements 1, the second and third channels of the switch 8,

Inputs B of the adder 5. The introduction of logical elements, NAND, OR three prohibition elements and two four-switch switches significantly expands the functionality of a universal redundant counter, makes it possible to use it as a multifunctional device with high reliability and reliability of stored information.

Operation mode

igpol 23 I 21 I 181 24 1 O 1 O 1 X at the exit

10 1 1 1 X the same

O 1 1 O O X

O 1 1 1 O X

11 1 X O X

X x o x x o tact

X x o x x input- same

ins

Note

In tact

element 13

on bus 22

NOAH

code

Claims (2)

Claims of Invention The counter containing the block of majority elements, the first, second and third registers and the equator, the outputs of which are connected to the inputs of registers, the outputs of which are connected to the input of the block of majority elements, with the aim of providing a reverse counting binary and decimal kodgis, elements I, I-N, OR first, vtschiey and the third elements of the first and second switches are entered into it, the outputs of which are connected to the input of the sumiator, the transfer input of which is connected to the output of the first element, The first and second control inputs of the switches are connected to the output 1 of the second and third prohibition elements respectively, the inputs of the second and third bits of the second channel of the first switch are connected to the output of the I element, the inputs of the second and third bits of the third switch of the first CS are connected to the output of the element NAND, the common bus is connected to the inputs of all the bits of the first channel of the first switch, the inputs of the first and fourth bits of the second channel of the first switch, and the inputs of all bits of the first and fourth channels to the first switch and the power bus are connected to the inputs of the first and fourth bits 5 of the third channel of the first coca | utator, the inputs of all the bits of the second and third channels of the second switch are connected to the outputs of the block of majority elements, the output of the OR element is connected to the clock inputs of aI registers, the first inputs of the OR element, the first, second and third prohibition elements are connected the counter reset input, and the second inputs of the OR element, the first, second and third prohibition elements are connected respectively to the write buses and the first, second and third control buses; the fourth control bus is connected to the first inputs The signals of the elements I and I-HB, whose octagonal inputs are connected to the outputs of the majority elements block, and the fifth, sixth and seventh control buses are connected to the first, second and third control inputs of the registers, respectively. Sources of information taken into account in the examination 1. USSR author's certificate 429536, cl. H 03 K 23/00, 1972. 2. Shigin A. G. Digital computers, M., Energie, 1971, p. 266, fig. 10-18 (prototype).