SU1636844A1 - Device for modulo addition and subtraction - Google Patents

Abstract

The invention relates to automation and computing and can be used in computers and devices operating in the system of residual classes. The purpose of the invention is to expand the functionality by obtaining the result of a modular multiplication operation. The goal is achieved by shaping the magnitude and sign of the shift

Description

ve ±

CE) 00 (35 00

Let

eleven

annular shift register 17 for the multiplication operation by introducing into the device containing the first 2 and second 10 decoders, first to third blocks 4, 7 and 16 elements AND, subtractor 5, first block 9 elements OR, receiving register 11, counter 12, circuit 13 comparisons, the first 14 and the second 15 prohibition elements,

ring shifting register 17, the first 18 and second 19 elements AND, the first, the second element OR 20, - the element NOT 22, the first encoder 24 and the group of elements OR 25, the second encoder 26, the second 33 and the third 31 elements: OR 33 and 31, second block 29 elements OR, fourth 27 and p

10 g- 6lokov Elentov I. 4 tab., 1 Il.

The invention relates to automation and computing and can be used in computers and devices operating in the system of residual classes.

The purpose of the invention is to expand the functional capabilities by obtaining the result of a modular multiplication operation.

The drawing shows a diagram of a device for adding and subtracting numbers modulo.

The device contains the first information input 1 of the device, the first decoder 2, the input information input 3 of the device, the first block 4 of the elements AND, the subtractor 5, the input 6 of the device module assignment, the second block 7 of the elements AND, the input 8 of the device subtraction, the first block 9 of the elements OR , the second decoder 10, the receiving register 11, the counter 12, the comparison circuit 13, the first prohibition element 14, the second prohibition element 15, the third block 16 And elements, the ring shift register 7, the first And 18 element, the second And 19 element, the first element OR 20, clock input 21 devices Real estate, element NOT 22, device output 23, first encoder 24, group of elements OR 25, second fourth block 27

the fifth block 28 elements AND, the second i 29 elements OR, the input 30 sets the device addition, the third element OR 31, the input 32 sets the device multiplication, the second element OR 33.

encoder 26-p- elements I9,

Consider the operation of the device in three modes. When modular operation, addition, (A + B) modm in binary code is performed, input 1 receives operand A, input 3 receives operand B, which also enters input of subtractor 5 (modulo t), output

five

0

h

Q

0

five

0

pogo get value (m-b). The signal from input 30 passes through the element OR 33 and opens the first block of 4 elements AND, through which and through the first block 9 elements OR operand B arrives at the input of the second decoder 10, From the output of the second decoder 10 operand B in the unitary code goes to the first the group of inputs of the first encoder 24, to the second group of inputs of which is fed through the first decoder 2 operand A. Depending on the ratio of operands A and B, a binary number is formed at the outputs of the OR elements of group 25, corresponding to the number of register shifts 17, and The OR 20 signal forms a signal if the shift direction is right (since the signal at the output of the OR element 31 is present, then the fourth block 27 of the AND elements is open). The signal from the output of the element OR 20 enters the first input of the element AND 18, and if there is no signal, then the element AND 19 opens, providing the left direction of the shift. From the entrance 21 to the openings of the Elements 14 and 15 of the prohibition, pulses arrive. When the states of the counter 12 and the receiving register 11 coincide, the comparison circuit 13 generates a signal that closes the inhibit elements 14 and 15 and opens a block of 16 AND elements, through which the value of the bit group of the register 17 (the result of the modular addition operation) enters the device output 23 .

Let it be necessary to determine the result (A-B) modm. In this case, the signal from input 8 goes to the second block 7 of the elements I. From the output of the subtractor 5, the value (t-8) through the open second block 7 of the elements is AND, the block of 9 elements (OR goes to the second decoder -1 10. Further operation of the device

logical to determine the result of the modular addition operation.

If the result (A tB) modm is determined, then a signal is present at input 30, which opens the first block 4 of the AND elements and the fifth block of the 28 I elements. In this case, the inputs of the OR 25 group and the first OR 20 elements receive information from the outputs the second encoder 26 through the fifth block of 28 AND elements and the second block 29 of the OR elements. Further work is similar to determining the result of a modular addition operation.

Consider examples of the specific implementation of the operation of modular addition of subtraction and multiplication for.

The initial state of the register is 17: 1-0-1-0-0-0. The first three bits correspond to the number 5. The number 3 corresponds to the shift of the register 17 to the left by one binary digit. 2 - to the right by one binary

bit, etc. Make a table for re-25 cops And goes to exit 23. This

Allocation of modular operation, Table. 1 shows the results of the modular addition operation.

In tab. 2 for building the encoder 24, the necessary number of shift cycles for each pair of operand is reflected. Dov A and B and the direction of shift, Shift to the left corresponds to the positive direction of shift and is reflected in the table. 2 sign +.

Create a table to implement the modular multiplication operation. Table 3 shows the results of the modular multiplication operation.

 In tab. 4, to construct the encoder 26, the required number of shift cycles for each pair of operands and the shift direction is reflected.

 Consequently, the group of elements OR 25, which performs the function of the encoder, consists of two elements that form four numbers: 00, 01, 11. 11. The OR-20 element combines the outputs of the encoder 24, or the encoder 26, which are sign - respectively, in. . tab. 2 and 4.

Example 1.,. You must define (A + B) modm. The first is the result of the operation.

Example 2.,, It is necessary to determine (A-Sjmodm. In this case, the first input of the second group of the first 30 encoder 24 receives a signal. The sixth input of the first group of inputs of the first encoder 24 also receives a signal () ./ In the receiving register 11, the number 00 will be recorded. The signal from the output of the element OR 20 is not received, and the comparison circuit 13 at the moment of turning on the device generates a signal closing the prohibition elements 14 and 15 and the opening block 16 of the elements AND, (no shift). register 17 will be as follows:

35

40

I

.L

I-0-I-I-0-0-0

3

The contents of the first three binary 45 bits of register 17 represent the result of the modular subtraction operation.

Example , It is necessary to define (AXB) modm. The first operand arrives at the first decoder 50 tor 2, from the output of which arrives at the third input of the second group of inputs of the second encoder 26, Operand B through the fourth block of 4 elements AND (the output signal OR 33 is present) the rand arrives at the first decoder 55 and first block 9 elements OR through torus 2, from the input of which the second decoder 10 enters the fourth input of the second group of inputs, the encrypted input of the first group of inputs of the second 24. Operand B through the first encoder 26. In the receiving register of 4 elements AND and the first block 9re 11 bu dat recorded number 10 sog0

0

elements OR goes to the second decoder 10. From the output of the second decoder 10 goes to the third input of the first group of inputs of the encoder 24. In the receiving register I1, the number 01 will be written according to the table. 2 (the signal from the output OR 31 opened the fourth block 27 of the elements AND). The signal from the output of the element OR 20 is not received, but the (element AND 19 signal is received. The pulses through the open elements 14 and 15 of the prohibition go to register 17 and to counter 12. At the moment of coincidence of state 5 of register 11 and counter 12 (in the counter

12 contains the value 01) scheme

13 compares the signal that closes the prohibition elements 14 and 15 and opens the third block 16 of elements I. The register state 17 will be as follows:

c1

0-1-0

I - I - 0 - From

The contents of the first three rosters of register 17, through the third block of 16 ae, is the result of the operation.

Example 2.,, It is necessary to determine (A-Sjmodm. In this case, the first input of the second group of the first encoder 24 receives a signal. The sixth input of the first group of inputs of the first encoder 24 also receives a signal () ./V the receiving register 11 will be recorded with the number 00. The signal from the output of the element OR 20 is not received, and the comparison circuit 13 at the moment of turning on the device generates a signal closing the prohibition elements 14 and 15 and the opening block 16 of the elements AND, (no shift). Register 17 will be the following:

I

.L

I-0-I-I-0-0-0

3

The contents of the first three bits of register 17 represent the result of the modular subtraction operation.

Example , It is necessary to define (AXB) modm. The first operand arrives at the first decoder 2, from the output of which arrives at the third input of the second group of inputs of the second encoder 26, Operand B through the fourth block of 4 AND elements (according to Table 4 (the signal is present at the second input of the fifth block of 28 AND elements) .

The signal from the output of the element OR 20 enters the input of the element AND 18, The pulses through the open elements 14 and 15 of the prohibition are fed to the register 17 and to the counter 12, When the state of the register 11 and the counter 32 coincides (in, the counter contains the value 10) Comparison generates a signal closing the elements 14 and 15 is forbidden and the opening unit 16 of the elements I. The state of the register 17 will be as follows:

QJ

1-0-0-0

about

D

The content of the first three bits of register 17 is the result of the modular multiplication operation JQ.

Claims (1)

Invention Formula A device for adding and subtracting modulo numbers, containing first and second decoders, subtractor, receiving register comparison circuit, counter, ring shift register, encoder,} from the first to third blocks of AND elements, first block of OR elements, first and second the prohibition element, the first and second elements AND, the group of elements OR, the first element OR and element 3 $ and the first information input of the device is connected to the input of the first decoder, the second information input of the device is connected to the first input of the first electric unit And with and the input of the subtracted subtractor, the input of the reduced and the output of which are connected respectively to the input of the device module and the first input of the second block of elements And the input of the device subtraction set is connected to the second input of the second block of elements And the outputs of the first and second blocks of elements And they are connected respectively to the first and second inputs of the first block of the OR elements, the output of which is connected to the input of the second decoder; the outputs of the receiving register and the sensor are connected respectively to the first and second inputs The comparison circuit, the output of which is connected to the control inputs of the first and second prohibition elements, with the first input of the third block of elements And, the inputs of the bits of the second input of which are connected respectively to the outputs 0 five Q five 0 five 0 five 0 five Iog2m + 1 (m modulus) the lower bits of the ring shift register, the left and right shift enable inputs of which are connected respectively to the outputs of the first and second elements AND, the output of the first element OR connected to the first input of the first element AND, the clock input of the device connected to information the inputs of the first and second prohibition elements, the output of the second prohibition element is connected to the counting input of the counter, the output of the first element OR is NOT connected to the first input of the second element AND, the second input of which Combined with the second input of the first element And and connected to the output of the first prohibition element, the output of the third block of elements And is the output of the device, the outputs of the second and first decoders are connected to the inputs of the first and second groups of the first encoder, respectively, the outputs of the elements OR are connected to the inputs of the corresponding bits The reception register, characterized in that, in order to extend the functionality by obtaining the result of the modular multiplication operation, a second encoder is introduced, the second and third elements you are OR, the second block of elements OR, the fourth and fifth blocks of elements AND, and the outputs of the second and first decoders are connected to the inputs of the first and second groups of the second encoder, respectively, the outputs of the first and second encoder are connected to the first inputs of the fourth and fifth blocks of elements, respectively And, the outputs of which are connected to the first and second inputs of the second block of the OR elements, the inputs of the addition and subtraction tasks of the device are connected respectively to the first and second inputs of the third element OR, the inputs of the addition and clever The devices are connected respectively to the first and second inputs of the OR element, the output of which is connected to the second input of the first block of elements AND, the output of the third element OR, and the input of the device multiplying the device are connected to the second inputs of the fourth and fifth blocks of the elements AND The terminals of the second block of the OR elements are connected to the corresponding inputs of the first element. ment OR or elements OR groups. 163684410 Table 1