SU1506505A1 - Frequency multiplier - Google Patents

Abstract

The invention relates to the field of radio engineering and communications and can be used in automation devices and computer technology. The purpose of the invention is to improve the uniformity of the distribution of output pulses. The frequency multiplier contains counters 1.2, frequency dividers 6.7, block 8 comparison of codes, RS - trigger 9, two elements AND 10, 11, two elements OR 13, 14. Three counters 3-5 are entered into the frequency multiplier, AND element 12, two inverters 15, 16 and rr 17 clock pulses. In order to obtain a uniform output frequency, the signal from the inverter 15 is fed to the counting input of counter 3, the transfer pulse of which provides for the change in the content of counter 1 by one. 1 il.

Description

SP U1

31506

The invention relates to radio engineering and communications and can be used in automation and computing devices.

The purpose of the invention is to increase the uniformity of the distribution of the output pulses.

The drawing shows a structural electrical frequency multiplier circuit.

The frequency multiplier contains the first 1, second 2, third 3, fourth 4 and fifth fifth counters, first 6

and second 7 frequency dividers, block 8

com (codes, RS-flip-flop 9, first 10, second 11 and third 12 elements. And, first 13 and second 14 elements OR, first inverter 15, second inverter 16 and clock generator 17.

The frequency multiplier works as follows.

The counting input of the fourth counter 4 receives a periodic sequence of pulses from the first generator output 17 clock pulses. The fourth 4 and fifth 5 counters measure the period of the input signal before the arrival of the next input frequency pulse, which zeroes the first 6 and second 7 dividers and sets the RS flip-flop 9 to one state. On the falling edge of the first pulse from the first generator of the 17 clock pulses at the output of the first divider 6, a single state is established, while the pulse from the second generator output of the 17 clock pulses is rewritten from the fourth: 4 and fifth 5 counters, respectively, to the third 3 and the first 1 counters, and the fourth and fifth 5 counters are zeroed by the pulse from the third output of the generator of 17 clock pulses.

The next pulse from the first generator output 17 clock pulses sets the zero state at the output of the first divider 6, and further state changes are blocked until the next input pulse arrives at the setup input of the first divider 6. The fourth 4 and fifth 5 counters measure the next input period signal. The code of the period of the input frequency, rewritten from the fourth 4 and n that 5 counter with

ten

five

0

i 30 Q

five

0

five

four

responsibly in the third 3 and first 1 counters, consists of two parts: whole - the contents of the first counter 1 and fractional - the contents of the third counter 3. The multiplier of the frequency multiplier is determined by the capacitance of the fourth counter 4. The code for the whole part of the period from the output of the first counter 1 arrives at the corresponding inputs of block 8, which compares the code of the integer part of the period with the code at the output of the second counter 2, to the counting input of which through the first element OR 13 pulses come from the first and third outputs of the 17 clock generator output pulses, i.e. the pulse frequency at the counting input of the second counter 2 is equal to twice the frequency of the generator 17 clock pulses.

At the moment when the codes of the outputs of the first 1 and second 2 counters are equal, an output pulse is generated by block 8 and the first 15 and second 16 inverters, which flushes the second counter 2 and the RS flip-flop 9. This results in the appearance of the first output pulse through a half-period multiplied frequency, which allows the frequency multiplier to have a stable multiplication factor, while decreasing each. period of the input frequency by 0.5 period of the multiplied frequency and with any increase in the period of the input frequency due to blocking the second counter 2 through the second element OR 14 when the second divider 7 is filled with a number of pulses equal to the multiplication factor. In order to obtain a uniform output frequency, the signal from the first inverter 15 is fed to the counting input of the third counter 3, the transfer pulse of which provides for a change in the content of the first counter 1 by one.

Claims (1)

Invention Formula Frequency multiplier, containing the first and second counters, the first and second frequency dividers, the code comparison block, the RS flip-flop, the first and second AND elements, the first and second OR elements, and the outputs of the first and second counters are connected to the Corresponding Information vhada A code comparison block, characterized in that, in order to improve the uniform distribution of output pulses, third, quarter and fifth counters, a clock generator, first and second inverters, and a third And are introduced, the first output of the clock generator being connected to a counting input the fourth counter, with the counting input of the first frequency divider and with the first input of the first element OR, the second output of the clock generator is connected to the first input of the first element And, the output of which is connected to the set full-time inputs of the first and third counters, the third output of the clock generator is connected to the first inputs of the second and third elements H, the second inputs of the first and second elements I - to the output of the first frequency divider, the second input of the third element H - to start the RS-trigger, the output of the second element I - with the installation inputs of the fourth and fifth counters, the outputs of which are connected to the corresponding information The third and first counters, respectively, enter the senior bit of the fourth counter with the counted input of the fifth counter, the output of the third element I with the second input of the first OR element whose output is connected to the counting input of the second counter, the transfer output of the third counter with control the input of the first counter, the counting inputs of the first and third counters with the output of the first inverter, whose input is connected to the output of the code comparison block, the output of the second frequency divider with the first input of the second IL element And, the output of which is connected to the setup input of the second counter, the output of the first inverter is connected to the input of the second inverter, the output of which is the output of the frequency multiplier and is connected to the second input of the second OR element, to the counting input of the second frequency divider and to the R input of the RS flip-flop The S input of which is connected to the setup inputs of the first and second frequency dividers and is the input of a frequency multiplier.