SU1501175A1 - Device for checking buffer storage units - Google Patents

Abstract

The invention relates to computing and can be used to build devices controlling blocks of the buffer memory of information processing systems. The aim of the invention is to increase the reliability of the control. The device for monitoring the buffer memory blocks contains the shaper reference codes 1, the comparison unit 2, the control unit 3, the OR 5 item, the first counter 7, the number 4 register, the second counter 6 and the memory block 8. The device provides control of the degree of hardware monitoring filling capacity of the buffer memory. 4 il.

Description

SL

ten

15

20

25

thirty

The invention relates to computing and can be used to build devices controlling blocks of the buffer memory of information processing systems.

The purpose of the invention is to increase the reliability of the control.

Fig; 1 shows a block diagram of the device; Fig. 2 is a block diagram of one of the embodiments of the control unit; FIG. 3 shows the structure of the control word j in FIG. 4 — timing diagrams of the operation of the control unit.

The device for monitoring the buffer memory blocks contains the shaper 1 reference codes, the comparison block 2, the control block 3, the register 4 numbers, the OR element 5, the second counter 6 and the first counter 7, the memory block 8, the start input 9, the outputs 10 boot data, input 11 of the control word record, input 12 of the installation, outputs 13,14,15 failure, verifiable. block 16 buffer memory. FIG. 1, the inputs and outputs of the control unit 3 are numbered, namely, outputs 17-24 and inputs 25-29.

One of the possible variants of the control unit 3 (FIG. 2) contains the triggers 30 and 31, the clock generator 32, the NOT element 33, the AND element 34, the counter 35, the desphrarator 36, the elements of the SRI 37.38, the triggers 39-42.

The device works as follows.

Before the start of operation, the signal at the installation input 12, the first counter 7, the triggers 30.31 and 39.40 of the control unit 3, the driver 1 of the reference codes and the checked buffer memory unit 16. are reset.

In the download mode of the control program 5, control words (data) are successively inputted to the load inputs 10 accompanied by a signal at the input 11 of the device, which writes the control word to memory block 8 at the address generated on the counter 7. Rear the front of the signal at the input 11 of the device, which has passed through the element OR 3, modifies the contents of the counter 7, i.e. unit is added to its contents. Each control word written to memory block 8 defines one component part of the pro40

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The control system contains the following functional parameters, namely:

A is the field defining the length of this composite part of the monitoring process and specified by the number of calls to: the scanned block of the buffer memory c; write operations — read data;

B - a field defining the types of operations performed and their temporal characteristics, containing two bits, the presence of a logical unit in each of which specifies the write and read operations, respectively, and contains bits that characterize the time. variable characteristics of the storage of information of the checked memory block;

C is a field defining the monitored parameters of this component of the check, including the permission to control information, the permission to control the correctness of the formation of signals of the buffer memory fill level, namely, the buffer is empty The buffer is full and intermediate states n-and, if such there are;

D - the field defining the synchronization of the operation of the driver of reference codes.5

0

Fig. 3 shows a control word, the specific content of which means the following:

-in field A (bits .0-7) contains - r c code 255, which defines the length

this part of the control process under the control of the control word;

-B field (bits 8, 9, 10) contains logical units, which determine, that in each elementary cycle (from zero to 255th) write operations (bit 8) and data reading (bit 9)., the unit in the 10th bit determines the specific duration of the write and read requests;

-C field (bits 11,12,13) contains the parameters that need to be controlled during the control process under the control of this control word, namely: control of the identity of the recorded and read information (unit in the 13th level), formation control Signal Buffer is empty at the end of control (one in 12th bit), no co-shaping of signal. Buffer is filled

None at the end of control (zero in the 11-m discharge);

- field D (bits 14,15) contains the permission of the shaper of reference codes (unit to 14 mraz. pd) and an indication of the reset to the initial state of the shaper of reference codes at the end of control (unit of 15- m ras de).

In memory block 8, K-2 control words are written to successively increasing addresses, where n is the size of the counter 7, defining K co 15

20

25

thirty

the common parts of the buffer storage unit check. In this mode, the loading of control words in the memory block 8 ends.

The control of the buffer storage unit 16 begins with the arrival of the signal at the start 9 input, which - with the falling edge sets the C-input trigger 30 to 1, sets the counter 35 to the zero state and triggers 41 and 42 via the OR 38 element. the differential signal 32 coming to the C input of the trigger 31, the high signal level will be overwritten into the trigger 31, which allows the clock pulses to pass from the output of the HE element 33 through the AND 34 element to the counting input of the counter 35. The signals from the bit outputs of the counter 35 are nar do with signals the triggers 41 and 42, the output of the comparison unit 2, the outputs of the fill level of the capacity of the tested block 16 and the second group of outputs of the memory block 8 are delivered to the information inputs of the decoder 36, the input signal of which is received from the output of the AND 34 element After the control word loading mode, the counter 7 is in a state that determines the address of the first control word in the memory block 8. Thus, at this moment in time, the first control word is present at the outputs of the first and second groups of the memory block 8, since the memory block 8 is in the read mode. Under the influence of the clock pulses of the generator 32, the counter 35 successively passes a state from

35

40

50

ABOUT

to 2, where 1 is the counter size 35. At the same time, at the outputs of the decoder 36, i.e. At the outputs of the control unit 3, the following control signals (FIG. 3 and 4) appear successively.

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five

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The signal on TibrxoAe 22, which writes the code of the length of this component of the test into counter 6 (subtractive counter) and with its falling edge on the C input, sets trigger one 42, which prohibits further generation of a signal at output 22 when working with remote control In a word, the Signal sets to one (. The state of the trigger 40 when there is one in bit 8 of the control word; the signal at output 19 enters the input of the tested block 16 as a request signal for recording information. After a time interval, a sufficient To perform the write operation by the verifiable unit 16, which is set by the signal level in the control word bit 10, a signal is generated that sets the trigger 40 to the zero state. After the write operation is performed, the signal from the decoder 36 output is set to one trigger 39 and the signal From output 20 it enters the input of the checked block 16 as a request for reading data. At a time interval sufficient for reading the data and determined by the control word bit 10, a signal appears at output 21, which is into register 4 read from the unit 16 verifies emogo data. A signal is generated that sets the trigger 39 to the zero state. The result of the comparison of the recorded and read data (if there is one in the bit 13 of the control word) is analyzed, and if there is a discrepancy, a fault signal is generated at the output 13 of the control. A signal is generated at the output 18 of the modification of the driver 1 of the reference codes, under the influence of which the following reference code is formed at the inputs of the thermally modifiable block 16.

A signal is generated at output 23, which reduces the content of counter 6 by one. The actions described above are repeated in each of the passes from 0 to 2 of counter 35 until the counter overflow of counter 6, i.e. at the input 29 of the synchronization unit, a signal does not appear that sets trigger one to 41, which indicates the end of control under the control of the given control word.

The signal level at input 25 is analyzed. Buffer is empty, since unit 12 is present in unit 12, and in the absence of a high signal level, the buffer is empty, a fault signal is generated at control output 14. A reset signal is generated from the code generator 1 to its initial state. 17 through the element OR 37; A signal is generated at output 24, which passes through the element OR 5 and increases by one the contents of counter 7, i.e. at the outputs of memory block 8, the next control word is set. The signal of the rabble of the trigger 41, which passes through the OR element 38, is formed, resets the trigger 42 to the zero state and, arriving at the C input of the trigger 41, sets it to the zero state with its falling edge.

In subsequent control words, when appropriate conditions are specified, the signal is monitored at input 26 (a high signal level at the output of the Buffer is full of the tested block), and if it is not present, a fault signal is generated at the control output.25. The control process of the control K of control words is performed until a signal appears at the input 12 of the installation, which sets the device to its initial state.

Claims (1)

Invention Formula A device for controlling buffer memory blocks, comprising a reference code generator, the synchronization input of which is connected to the first output of the control unit, the outputs of the reference code generator are information outputs of the device, the first counter, the OR element and the comparison unit, characterized in that, in order to increase the reliability control, a number register, a second counter and a network unit are entered into it, the information inputs of the register being the first information inputs of the device, the outputs of the register of the number of They are not connected to the first inputs of the comparator unit, the second inputs of which are connected to the outputs of the reference code generator, the installation input of which is connected to the second output of the control unit, the third and fourth outputs of which are the recording enable and readout outputs of the device, the fifth and sixth outputs of the unit the control is connected respectively to the input of the record of the number register and the first input of the OR element, the second input of which is connected to the control input of the memory block and is the input of the control word of the device, the second information inputs of which are connected to the information inputs of the memory block, whose address inputs are connected to the outputs of the first counter, the counting input of which is connected to the output of the OR element, first & the group of outputs of the memory block is connected to the information inputs of the second counter, the input Records and counting inputs of which are connected respectively to the seventh and eighth inputs of the control unit, ninth, tenth and eleventh outputs of which are the first, second and third outputs of the device, the installation input of which is connected to the installation input of the first counter and control unit The second group of outputs of the memory unit is connected to the inputs of the command of the control unit, the error input of which is connected to the output of the comparison unit, the inputs of the degree of filling of the device connected to the inputs, respectively. Buffer empty and the buffer is filled by the control unit, the overflow output of the second counter is connected to the input End of the control of the control unit, the start input of which is the same input of the device. isa and aa 1) 14 fJttijfiaaff Paspsffb / 0123 55189 10 11 11 1 $ 14 15 F1I.1 tt a