SU1501167A1 - Buffer storage - Google Patents

Abstract

The invention relates to computing and can be used in processing information in the order of its receipt from subscribers, for example, in computers when performing the functions of servicing a large number of peripheral devices, in data transmission multiplexers for accumulating discrete information coming from communication channels, or computer network adapters. The aim of the invention is to expand the field of application by providing operation in the mode with preliminary accumulation of a data block of arbitrary length. The buffer storage device contains the first 1 and second 2 elements AND, triggers 3-6, the first 7, the second 8 and third 9 AND-NOT elements, the register 10, the first 11 and the second 12 comparison blocks, the write address counters 13 and the read address 14, multiplexer 15 and drive 16. 1 Il.

Description

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The invention relates to computing and can be used as a storage device in processing information in the order received from subscribers, for example, in computers when performing the functions of servicing a large number of peripheral devices in data multiplexers for accumulating discrete information from channels. communications, or in computer LAN adapters.

The purpose of the invention is the expansion of the field of application due to the provision of work in the mode with preliminary accumulation of a block of data of any arbitrary rate.

The drawing shows a block diagram of the device.

The device contains the first 1 and second 2 elements AND, the first 3, the second 4, the third 5, the fourth 6 triggers, the first 7, the second 8, the third 9 AND-NOT elements, the register 10, the first 11 and the second 12 comparison blocks, the counter Addresses of record 13 and read 14, multiplexer 15, accumulator 16, information 17 inputs and outputs 18 of the device, synchronization input 19, write request input 20 20, read request input 21, input 22 end of block write, write response output 23, answer 24 reading, exit 25 end of reading block.

The conversion factors of counters 13 and 14 are the same and equal to the information capacity of the storage device liB, which in turn must exceed the maximum data block. Triggers 3 and 4 switch on different fronts of signal 19. Triggers 5 and 6 have inverse inputs for asynchronous setting and reset. Register 10 and counters 13 and 14 are triggered on the negative front of the clock signals.

The device works as follows;

In the initial state, the register as well as all the triggers and counters are reset. The process of recording and reading is synchronized by a TI 19 signal with a repetition time of imyuls equal to the duration of writing to the accumulator 16. The address of the accumulator receives the contents of counter 13, and the W / R input is a logic level of O.

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logic signal O, indicating the absence in the drive 16 pre-prepared data block. The passage of the pulse 34T 21 through the element 2 is blocked.

In the process of operation of the OVC, the inputs 20 and 21 can independently receive: t pulse ZZP, pulse 341, both pulse ZZP and 341.

In the case of the arrival of a pulse of the backup transducer, it passes through the unlocked element I 1 and is stored in trigger 3. In this case, the passage of 34T through element 2 is set, trigger 5 is set, a logical signal 1 is sent to the W / R input of the accumulator, a response signal is output into the external environment, after which it is possible to remove the input signal of the RFP. Then, the passive level of the CRP signal is remembered in trigger 3.

This stops the recording of the number in the accumulator 16, increments the counter 13, which now points to the address of the next recording cycle, unlocks the element 2.

The mounted trigger 5 permits the passage of the signal from the comparator unit 11 through the element 7, which blocks the transfer factor in the event that the accumulator is filled after the write cycle.

If a signal was sent in the write cycle, CPLC 22 (write the last word of the data block), then the signal from the output of element 9 in register 10 latches the address of the last write cycle, sets trigger 6, and as a result, unlocks element 2 and outputs signal 25, indicating about the availability of the finished block of data in the hopper 16. 1

In the event of a pulse

34T at the input 21, the number is read from the address determined by the counter 14. The reading cycle is similar to the write cycle. By the end of the reading cycle, counter 14 is increased; trigger 6 is reset, so that the output of the comparator unit 12 is connected through element 8 to the input of element 2 and, after reading the last word of the previously prepared data block, blocks the passage of the 34T signal and also causes the appearance of the Q4BP signal (the end of the block reading) 25; the trigger is reset, as a result of which Pr 1 is allowed to pass the RFP 20 signal through element 1.

In the case of simultaneous arrival of 34t pulses and a ЗЗП due to the fact that triggers 3 and 4 subptagot on different fronts of TI19 clock pulses first change their state, for example, trigger 3, while a recording cycle occurs, passing 34T to trigger 4 is blocked until end of write cycle.

At the end of the recording cycle, the signal 34t passes through element 2 and is written to trigger 4. A reading cycle occurs.

This is how conflicts are resolved when writing and reading requests are made at the same time.

Claims (1)

Invention Formula A buffer storage device containing a write-address accumulator-counter and a read-address counter, a multiplexer, the first and second trigamers, the first and second AND elements, the first inputs of which are the read request and the read request of the device, the outputs of the first and The second elements And are connected to the information inputs of the first and second triggers, respectively, the forward outputs of which are connected respectively to the synchronization inputs of the write and read address counter and are the write and read response outputs The devices, information inputs and drives accumulators are respectively information inputs and outputs of the device, the inverse output of the first trigger is connected to the secondary input of the second element Ir, the inverse output of the second trigger is connected to the second input of the first element I, the clock inputs of the first and second trigger are combined and are the device's synchronization inputs, the accumulator address inputs are connected to the multiplexer outputs, the information inputs of the first group of which are connected to the output Q d 0 5 o Q 5 five 676 Dami write address counter, information inputs second gr | T1Ps of the multiplexer Connected to the outputs of the reading address counter, characterized in that, in order to expand the scope of application due to the possibility of operating in the mode with preliminary accumulation of a data block of the derived length, the first and second comparison blocks, the register, the third and fourth quarter triggers, the first , the second, third AND-HEj elements, the outputs of the write address counter are connected to the inputs of the first group of the first comparison block and the information inputs of the register, the outputs of which are connected to the inputs of the first group of the second block compared tim, whose output is connected to a second input of the second AND-NO element whose output is connected to a third input of the second: element. And it is the output of the reading end of the device block, the outputs from the read address cetcher are connected to the inputs of the second group of the second and first comparison blocks, respectively, the output of which is connected to the first input of the first AND-NOT element, the output of which is connected to the third input of the first control element the multiplexer input is connected to the forward output of the second trigger, the forward output of the first trigger is connected to the second input of the third AND-II element and the drive mode job input the first input of the third li-HE element is the input End device block records, the output of the third AND-NOT element is connected to the installation input to the unit state of the fourth trigger and the register synchronization input, the inverse output of the second trigger is connected to the installation inputs to the third and fourth triggers, the inverse output of which is connected to the first the input of the second element IS-NOT direct output of the third trigger is connected to the second input of the first element IS-NOT, the inverse output of the first trigger is connected to the input of the output / output unit in the single state of the third flip-flop.