SU1499466A1 - Pulse duration selector - Google Patents

Abstract

The invention relates to a pulse technique and can be used in communication devices for selecting pulses by duration and determining the nature of distortions of selectable pulses. The pulse selector includes a generator of 1 clock pulses, triggers 2, 3 and 15, counters 4 and 5 pulses, a decoder 6, drivers 7 - 9 pulses, elements 10–12, 18–20, an element OR 13, a divider 14 frequencies, the register 16, the HE element 17, the input buses 21 and 24, the output buses 22 and 23. Ensuring the possibility of selecting pulses with a duration greater than and less than the set one and obtaining information about the magnitude of the deviation of the pulse duration from the set allows expanding the functionality of the device, and the device is operational when change wiring speed. 1 hp f-ly, 2 ill.

Description

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The invention relates to a pulse technique and can be used in devices for selecting pulses by duration and determining the nature of distortions of selectable pulses.

The purpose of the invention is to expand the functionality by enabling the selection of pulses with a duration of more and less than a given one and obtaining information about the magnitude of the deviation of the pulse duration from the given one.

FIG. 1 shows a structural electrical selector circuit; in fig. 2 - time diagrams that show his work.

The pulse selector contains the generator of 1 clock pulses, the first trigger 2, the second trigger 3, the S input of which is connected to the overflow output of the first counter of 4 pulses, and the R input to the reset input of the second counter of 5 pulses. The outputs of counter 4, bitwise, are connected to the inputs of the decoder 6 .. The S input of the trigger 2 is connected to the output of the first driver 7 pulses, the input of which is connected to the input of the second driver 8 and pulses, the output of which is connected to the reset input of the counter 5. whose overflow input connected to the input of the third shaper 9 pulses. The clock inputs of counters 4 and 5 are connected to the outputs of the first 10 and second 11 elements, respectively. The output of the imaging unit 9 is connected to the first input of the third element And 12, The outputs of the counter 4 are bitwise connected to Hbj, to the inputs of the element OR 13. The output of the generator 1 connected to the input of the divider frequency 14. The first and second control inputs of the counter 4 are connected respectively to the inverse and direct outputs of the third trigger 15. The output of the element 12 is connected to the control inputs of the decoder 6 and the register 16 the input of the former 7 is connected to the input of the element 17. The output of the element OR 13 is connected to the first input the fourth element -AI 18 and the second input of the register 16. The output of the imaging unit 8 is connected to the first input of the fifth element And 19. The output of the element OR 13 is connected to the first input of the element And 20. The input of the imaging unit 7 is connected to the first input4yy bus 21, outputs

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decoder 6 form the first output bus 22, the outputs of the registers 16 - the second output bus 23, and the control inputs of the divider 14 - the second input bus 24. The output of the divider 14 is connected to the first inputs of the elements 10 and 11, the second inputs of which are connected respectively to the input bus 21 and trigger output 2. The overflow and borrow outputs of counter 4 are connected respectively to the S- and first R inputs of the trigger 15, the second R input of which is connected to the input and output of the reset of counter 4 and the output of element 19, the second input of which is connected with the second input element And 11, t This input is connected to the output of the element NOT 17. The output of the trigger 3 is connected to the second input of the element 12, Inverse and direct outputs of the trigger 15 are connected respectively to the second inputs of the elements 18 and 20, the outputs of which are connected respectively to the first and third register inputs 16.

The selector works as follows.

In the initial state, the counters 4. And 5 are in the zero state, the triggers are 2,3,15 and 16 resetters.

The clock pulse generator 1 outputs a sequence of clock pulses which is fed to the input of divider 14. The division factor of divider 14 is selected by applying a binary combination to its control inputs on bus 24, depending on the speed of the input pulses so that the filling time of counter 4 at a given wiring speed is half the duration of the reference pulse).

Upon arrival on the bus 21 of an elongated burst of pulses consisting of two pulses (Fig. 2.1a), the shaper 8 pulses along the front of the input parcel generates a pulse (Fig.2, Pro), which zeroed the counter 5, trigger 3, and , the passage through the element 19, opened at the second input, zeroed the trigger 15 and the counter 4, if the indicated elements in the process of operation were not in the zero state; At the first instant of time being considered, this pulse of the state of the indicated elements does not change, since they are in the zero state.

Under the influence of the input pulse, the element AND 10 opens and the clock input of the counter 4 begins to receive the clock pulses (Fig.2.2a). Since the first control input - counter 4 from the inverted output of the trigger 15 is affected by a positive potential (Fig. 2.11a) , then counter 4 performs summation of the clock pulses arriving at its clock input. As the counter 4 is filled (which is determined by the half of the duration of the reference parcel), the latter generates an overflow pulse at its overflow output (Fig. 2.9a), which sets trigger 3 into a single state and, entering the S-input of trigger 15, translates it also in a single state. As a result, the unit potential (Fig. 2.1 Za) from the direct output of the trigger 15 acts on the second control input of counter 4, which begins to subtract from the maximum number (equal to the volume of the counter) recorded in counter 4, the clock pulses that continue to flow to it clock input

As soon as counter 4 clears, a zeroing pulse appears at its exit of the loan (Fig. 2.10a), which places the trigger 15 in the zero state (Fig. 2.136) and the unit potential from the inverse output of the trigger 15 (Fig. 2, 11 b) again switches counter 4 to the summation mode. An overflow pulse (FIGS. 2, 96) from the overflow output of counter 4 (when it is filled) translates trigger 15 into a single state (FIG. 2.1 Over), as a result, counter 4 begins again to subtract the clock pulses from the maximum volume its clock input.

As it zeros, counter 4 imposes an impulse (fig. 2, 10b) on its borrow output, which triggers trier 15 to the zero state, (fig.2, 13 g), as a result, the counter again begins to count clock pulses received at its clock input until the input is complete (Fig. 2.1a and 2a) ..

Cutting the input parcel, the pulse former 7 generates a pulse (Fig. 2.4a), which, arriving at the S input of the trigger 2, translates it into a single state (Fig. 2.5a). So from the output of the element NOT 17 to TDB0

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the input element of the element 11 (Fig. 2,8a), a single potential effect, the element 11 and turns out to be open and clock pulses appear on its output (Fig. 2.6a) arriving at its first input from the output divider 14. Counter 5 counts the clock pulses arriving at its clock input from the output of element 11, until it overflows (the filling time of counter 5 is equal to half the duration of the elementary reference parcel).

As the counter 5 overflows, the latter delivers a single potential to its overflow output, on the front of which the pulse shaper 9 will generate a pulse (FIG. 2, 7a), which sets trigger 2 to the zero state (FIG. 2.56) and entering the first input of the element H 12 passes to its output, since on the second input element H 12 is opened by a single potential from the output of flip-flop 3 (which is set by an overflow pulse from the overflow output of counter 4).

From the output of element 12, this pulse arrives at the control inputs of the decoder 6 and register 16. As a result, the output of the decoder 6 records in decimal form the amount of deviation of the duration of the input pulse from the specified one, affecting the binary code 6 to the inputs of the decoder. Register 16 is three D flip-flops with a common control input. Its second input from the output of the element 1Sh 13 (since the counter 4 is not in the zero state) is affected by a single potential and the first input is also affected by the output of an AND 18 unit potential, since both inputs of the element And 18 are supplied by single potentials : one from the output of the element OR 13, and the second from the inverse output of the trigger 15.

As a result of the pulse on the control input of register 16, a single potential appears at its first output (since the second output is inverse, and the third input of the trigger 16 has a zero potential), which indicates that the input signal elongated (Fig. 2,12a).

When a pulse interference is applied to the bus 21 of the device (Fig. 2.1 b), the driver 8 generates a pulse along the front of the input pulse (Figure 2, 3b), which zeroes the counter 5 and the trigger 3 and through the open element I 19, trigger 15 and counter 4. Last during the action of the pulse interference, the counter 4 then counts the clock pulses arriving at its clock input. In this case, the operation mode of the counter 4 and the trigger 15 is similar to that considered. At the end of the impact of the input pulse, the trigger 15 is in a single state (Fig. 2, 1S), and after

reads the number of clock pulses Q pulse to the control inputs of the register 20

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owls (fig. 2.26) arriving at its clock input. By the cutoff of impulse noise, the pulse shaper 7 generates a pulse (Fig. 2.4b), which converts trigger 2 into a single connection (Fig. 2.5). As a result, the counter 5 begins to count the pulses arriving at its clock input from the output of the element 11 (Fig. 2.6b) -. As the overflow occurs, the counter 5 delivers a single potential to its overflow output, on the front of which the pulse former 9 generates a pulse (Fig. 2, 76), which triggers trigger 2 to the zero state and enters the first input of the And 12 element, which through the second input is closed. This completes the effect of impulse noise.

Consider the operation of the pulse distortion analyzer when a burst of pulses arrives at its input, consisting of three of them and prone to regional distortion (shortening) and crushing type distortion (Fig. 2.1c).

On the front of this premise, the shaper 8 generates a pulse (FIG. 2, Sv), which zeroes counters 4 and 5 and triggers 3 and 15 (as indicated). Counting 4 starts counting the clock pulses received at its clock input (Fig. 2.2c). In the event of the occurrence of the use of a slit type split-by-slice on the single bus on the bus 21, the pulse shaper 7 generates a pulse (Fig. 2.4 V), which translates trigger 2 into a single state. Counter 5 during the operation of this distortion counts the clock pulses coming from the output

Paragraph 16 and decoder 6 a unit potential appears at the third output of the register. 16 (fig. 2.14a), if the poles are elongated — at the first output of the register 16 (figs, 2.12a), and if the duration of the input parcel is equal to or a multiple of the reference one, a single potential appears at the second (inverse) output of the register 16, since by the time of the pulse on the control input of the register 16, the zero potential is acting on its second input from the OR 13 output.

Thus, in comparison with the known, the proposed selector allows the selection of pulses, and a burst of pulses in duration, fixing the distortions and their magnitude, and their work is not affected by pulsarine disturbances, as well as distortions such as pulse splitting. When changing the speed of wiring, the selector remains operable, while it is necessary to change the division factor of the divider 14.

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Claims (2)

1. Pulse selector in duration, containing a clock pulse generator, the output of which is connected to the first input of the first element AND, the output of which is connected to the clock input of the first pulse counter, which is reversible, and the output of the clock generator is also connected to the first input of the second element And, the output of which is connected to the clock input of the second pulse counter, and the second input - to the output element And 11 (Fig. 2,6v). At the end of the first trigger, the S-input of which The scientific research institute of influence of the distortion type crushing shaper 8 generates a pulse (Fig. 2.3g), which zeroes the counter 5 and the trigger 3 and does not reach the output of the element AND 19, since its second (inverse) input is affected by the unit potential from the output of the trigger 2 (Fig. 2.5 g). As a result co55 One with the output of the first pulse driver, the input of which is connected to the input bus and the input of the second pulse driver, the output of which is connected to the R input of the second trigger and the reset input of the second pulse counter, the overflow output of which is connected to the input of a third Paragraph 16 and decoder 6 a unit potential appears at the third output of the register. 16 (fig. 2.14a), if the poles are elongated — at the first output of the register 16 (figs, 2.12a), and if the duration of the input parcel is equal to or a multiple of the reference one, a single potential appears at the second (inverse) output of the register 16, since by the time of the pulse on the control input of the register 16, the zero potential is acting on its second input from the OR 13 output. Thus, in comparison with the known, the proposed selector allows for the selection of pulses, and a burst of pulses by duration, while fixing the distortions and their magnitude, and their work is not affected by pulsed disturbances, as well as distortions such as pulse splitting. When changing the speed of wiring, the selector remains operable, while it is necessary to change the division factor of the divider 14. Invention Formula 1. Pulse selector in duration, containing a clock pulse generator, the output of which is connected to the first input of the first element AND, the output of which is connected to the clock input of the first pulse counter, which is reversible, and the output of the clock generator is also connected to the first input of the second element And, the output of which is connected to the clock input of the second pulse counter, and the second input - to the output first trigger whose S input with One with the output of the first pulse generator, the input of which is connected to the input bus and the input of the second pulse driver, the output of which is connected to the R input of the second trigger and the reset input of the second pulse counter, the overflow output of which is connected to the input of the third pulse generator, the output of which is connected with the first input of the r-retego element H, and the outputs of the first pulse counter are bitwise connected to the information inputs mi decoder, as well as an NL element and an output bus, which is different from the fact that, in order to expand the functionality due to | Q to ensure the selection of pulses with a duration longer and shorter than the specified one and to obtain information about the magnitude of the deviation of the pulse duration from the specified one, from the fourth 5th to the sixth elements And, the element NOT, the register, the third trigger and the second output bus, which is formed from the first to the third register outputs, the first to the third inputs of which are connected to the outputs of the fourth AND element, OR element and sixth AND element, and the first inputs of the fourth and sixth AND elements are connected to the output of the OR element, and 25 second inputs to the inverse and direct outputs of the third trigger, respectively, as well as to the first and second control inputs of the counter pulses, the outputs of which are bitwise connected to the inputs of the element OR, the output of the loan is connected to the first five | Q 20 25 ten The R-bypass of the third trigger, the overflow output — with the S inputs of the second and third triggers, and the reset input — with the second R input of the third trigger and output of the fifth And element, the first input of which is connected to the output of the second pulse shaper, and the second input with the output of the first trigger, the R input of which is connected to the output of the third pulse driver, the second input of the first element I connected to the input bus and the input of the element, nta, the output of which is connected to the third input of the second element I, the output of the second trigger connected to the second input The third element is And, the output of which is connected to the control inputs of the register and the decoder, the outputs of which form the first output bus. t 2. The device according to claim, 1, characterized in that, in order to ensure prompt change in the threshold for comparing the pulse duration, a frequency divider is inserted in Hfero connected between the output of the clock generator and the first input of the first element I, and the control inputs of the frequency divider form the second input bus.