SU1495808A1 - Two-processor computer system - Google Patents

Abstract

The invention relates to computing and can be used in control systems. The purpose of the invention is to improve the performance of a computing system by implementing the appearance of information by processors along two independent lines m. A two-processor computing system contains two processors, two memory blocks, two decoders, two triggers, a register, three bidirectional drivers, element 2И-OR, four elements And the four elements OR. 1 il.

Description

The invention relates to computing and can be used in control systems.

The purpose of the invention is to increase the performance of a computing system by implementing the exchange of information by processors along two independent magistrates.

The drawing shows the functional scheme of a micro-computer.

The microcomputer contains microprocessors 1 and 2, elements IZ, 4, 6, and 7, elements OR 5, 8, 9, and 10, element 2I-OR 11, bidirectional drivers 12–14, decoders 15 and 16, triggers 17 and 18, buffer register 19, memory blocks 20 and 2, groups of external devices 22 and 23.

In the initial state, the triggers 17 and 18 are reset. Logic O from their outputs enters the inputs of the Capture Processors 1 and 2 and initiates signals of the logic O at the outputs of the Acceptance Capture. brain teaser

About with outputs Confirmation of the capture of processors 1 and 2 is received at the inputs of elements And 6 and 4 and close them. From the outputs of the elements And 4 and 6 logical About come to the inputs. the element OR 9, and from its output - to the input of the sample of the bidirectional driver 14, lock it and set a high impedance state on both groups of inputs and outputs. As a result, the microprocessor data lines 1. and 2 are separated and acquire independent states. In addition, logical O from outputs Confirmation of the capture of processors 1. and 2 arrive at the input of the element OR 5, from the output of which to the input of the sample of drivers 12 and 13 and sets a high-impedance state at their inputs-outputs. In such a sharp processors can work simultaneously, each with its own part of external devices, and their total number is 2, where M is the bit size

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Master 11a. | gi addresses. Ilporieccnp mg ZHet appraised to your extra devices with O, and grogoressor 2 - pr А 1, Thus, each processor has a HF external devices connected to the computing system, and the devices connected to the first processor have addresses from O to 2 and to the second - from (1) to 2 L

After each i pouecci.:ip is turned on, it performs self-test test programs recorded in the charger. In the case of all KaJKpj ift test checks, the instructor issues a health register to the buffer register 19 (log.1 in the old data highway) and during a control period of time, it waits for a health message from another processor. Such a message will be absent if the tests are not performed. In this case, the healthy processor issues the Trunk Capture command of the faulty processor (log. 1 in the low-order data highway to trigger input 17 or 18). The trigger 17 (18) is set to one. Log, 1 from the trigger output 17 (18) enters the capture input of the faulty processor, for example 2, after which the group of address moves of the AO-Al address, reading and writing, and building the information input-outputs D (-D transition into high impedance the output state of gating external devices takes the value of the log. 0 grip - log,

The logical output from the gating output of the processor 2 locks the ILE 6 and 7, and the logical 1 from the output Confirmation of the capture returns AND 4, permits the passage of the signal Read from the output of the processor through the element 2I-OR to the switching input of the imager 14,

and the confirmation output is for 1 T |

In addition, the logical

coming from the output of the element OR 5 to the sample inputs of the drivers 12 and 13, opens them in the direction of transmitting HeHcnpaBHONry signals to the processor 2, since their switching inputs have a logical O with a processor capture 1,

The appeal of processor I to the group of external devices of processor 2

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and logical 1 at the output of the captured processor 2. Under these conditions, at the output a logical 1 appears and 1) the element OR 10 post pads on the gating input of the decoder 16, whose address is given by the address via the driver 12 from the group of outlets x; n;) Processor 1. Form 4, an open logical 1 at the output of the sample, coming from the output of the AND 4 element through the OR 9 element, switches the direction of information transfer by the input or output commands of the processor 1 in accordance with the state of the switching O input, to which the signals Controls from the output of the CPU through the element 2I-OR 1 1.

Thus, external devices of the faulty one are connected to a working microprocessor.

It is possible to access the memory of a faulty processor, provided that the address space of this memory does not intersect with the address space of a working processor. In the memory 20 and the memory 21, an area is allocated that contains programs for controlling the external devices of the disconnected processor. Thus, both the memory 20 and the memory 21 contain progamms for controlling the complete set of external devices, however, only in emergency cases (no message on the test execution) does the non-operational processor go to the external device control program after it has been disconnected.

Claims (1)

Invention Formula A two-processor computing system containing the first and second processors, the first memory block, characterized in that, in order to improve the performance by implementing information transmitted by the processors along independent mainlines, it additionally composes the iT second memory block, first through fourth elements And, first through fourth elements of the RTO, element 2I-I. G1I, first to third bidirectional drivers, first and second decoders, register, first S. 1 And rrri. the output of the first processor is connected to the inverse input of the first and first inputs of the second emitters, and the output of the indication of access to external devices of the first processor is connected to the right input of the first and second inputs of the second emitters H, the output of the sign of access to the memory of the first processor and connected to the sampling input of the first memory unit, the output of the first And element to the first input of the first RSHI element, the output of which is to the gate input of the first decoder, the output group of which is the first group of system outputs for connecting to the input inputs of the I / O devices the first group, the output of the information output feature of the first processor is connected with the recording input of the memory unit, with the first input-output of the second bidirectional imager, with the first input of the register recording and with the first output of the system for connecting nor to the inputs of the output information sign of the I / O devices of the first group, the output of the input information sign of the first processor is connected to the read control input of the first memory block, with the second input output of the second bi-directional driver, with the second output of the system for connecting to the output inputs of the input device -the output of the first group and the first input of element 2И-OR, the second input of which is connected to the third input-output of the second bidirectional driver, with the second input of the register entry, to the control input writing the second memory block, with the third output of the system for connecting the inputs of the information input feature to the I / O devices of the second group and with the output of the information output feature of the second processor, the output of the information input feature of which is connected to the read control input of the second memory block, with the fourth exit of the system for connecting to the inputs of a sign of output information of input-output devices of the second 5808 .6 groups, s. CHOTVERTMM RHO CHOM-gp.KHOD P In 1 progrvorr l ts.m. and with a read input of the register, group T, the course of the sampling is about: with the siphro input of the first tripra and c); toM of the first TT orp, t-rupp it |} orma- iU-iOHi bix inputs the processor outputs are connected to the first group of iQ system inputs / outputs for connection to the information inputs of the input devices of the first group, to the group of information and ion inputs and outputs of the first memory block and 15 group of the first inputs-outputs of the third bidirectional junction 5 and the younger and old bits of the group of information inputs-outputs of the first processor are connected 20 respectively with the information input of the first trigger and the first information input / output of the register, the second input of which is connected to the synchronous input of the second trigger and the output of the second decoder, the output group of which is the second group of outputs of the system fy for connection to the inputs of the input device selection output of the second group The 30th group of informational inputs-outputs of the second processor is connected to the group of informational inputs-outputs of the second memory block, to the second group of system inputs-outputs for  connection to information inputs- Jo to the outputs of input-output devices of the second group and with the second group of informational inputs-outputs of the third bidirectional driver, with 4Q than the younger and oldest bit group: information inputs-outputs of the second processor are connected to the information input of the trigger and the second information input (output g home-register output, the input sample of the third bidirectional driver is connected to the output of the second element OR, the first input of which is connected to the second input of the first element c, ment And, and to the output of the third element 17 This AND, the first direct input of which is connected to the output of the sign of access to external devices of the second processor and to the first input of the fourth (- that element AND whose output is connected to the first input of the third OR element, the output of which is connected to the gate input of the second decoder, information the KOTCI input is connected to the BXC / UIM address of the second memory block, to the second one-to-one input of the first two-side driver and to the address output of the second processor, where the high-order bit of the output output of the second processor is connected with the second inputs 1-gi of the fourth element I and the inverse input of the third element I, the second direct input of which is connected to the first input of the fourth element IL-, to the control input of the forward direction of the riepsoi o and the second bi-directional formers and the third input of element 2I-ISH1, the fourth input of which is zin with the output of confirmation of the seizure five the second input of the .4eTisejrroro element OR and the third input (M iJTOpciro of the AND element, the icoTOporo output is connected to the second inputs of the second and Tperbfii - o of the IPI elements, the output of the four-sided OR element is connected to the sample inputs of the first and second double lines) Formers, powering the 2I-I.SH-1 is connected to the control input of the direction of transmission of the third bi-directional former, the outputs of the first and second triggers are connected, respectively, with the inputs of the seizure feature of the second and first traversal: a memory coupled to the second processor, the second input of the sampling unit pam.ch um, PROCESSOR-L .. ... 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