SU1495746A1 - Prgram process control device - Google Patents

Abstract

The invention relates to computing and automation and can be used in the construction of programmable controllers, devices and software process control systems. The purpose of the invention is the expansion of the field of application based on the implementation of dynamic stop and the advancement of processes. The device for software control contains an address memory block, a memory block, a stack memory block, an address register, an address counter, a linear sequence length counter of nano commands, two stack depth counters, a synchronization counter, two stack depth decoders, a synchronization decoder, two latching trigger tags, trigger trigger, setup trigger, two control triggers, oscillator, one-shot, OR block of elements, modulo two block of elements, AND, OR, NAND, delay. 2 Il.

Description

i (21) 4293628 / 24-24. (22) 08/03/08 (46) 07/23/89. Bksh. № 27 (72) V. A. Melnikov, A. B. Digoran, A. D. Rajewski and Yu. M. Biryukov (53) 621.503.55 (088.8)

(56) USSR Copyright Certificate No. 1238035, cl. G 05 B 19/19, 1984.

USSR Author's Certificate No. 1328795, cl. G 05 19/417, 1986. (34) DEVICE FOR SOFTWARE CONTROLLED1} I AMATEHNOLOGICAL PROCESSES

(57) The invention relates to computing and automation and can be used in the construction of programmable controllers, devices and software process control systems.

The purpose of the invention is the expansion of the field of application based on the implementation of dynamic stop and the advancement of processes. Device for; software control contains address storage bdg, memory block, stack memory block, address register, address counter, nanocomand linear sequence length counter, two stack depth counters, synchronization counter, two stack depth decoder, synchronization decoder, two tag latching trigger, trigger trigger, setup trigger, two control triggers, generator, one-shot, block of OR elements, block of sum elements modulo two, AND, OR, AND-NO elements, deceleration. 2 Il.

SP

The invention relates to automation and computing technology and can be used in the construction of programmable controllers for devices and software control systems, as well as process control systems.

The purpose of the invention is the expansion of the field of application based on the implementation of dynamic stop and the advancement of processes.

The essence of the invention is to increase the performance of the device by quickly copying a linear sequence of control commands and using their copies in the flexible mode of controlling two processes.

FIG. 1 shows the functional scheme of the device for software

process control; in fig. 2 is a functional block stack memory diagram.

The device dp software process control (Fig. 1) contains the address memory block 1, memory block 2, stack memory block 3, instruction register 4, logical condition register 5, address register 6, address counter 7, linear length counter 8 nano-command sequences, first stack depth counter 9, second stack depth counter 10, counter 11 synchronization, first decoder 12 stack depth, second decoder 13 stack depth, synchronization decoder 14, first 15 and second

16Triggers fixation tags, trigger

17start, first 18 and second 19

yi

WITH

sd |

four

05

3: j49

control triggers, setup trigger 20, clock pulse generator 21, oscillator 22, block of elements OR 23, first 24, ninth 25, and eleventh 26 elements OR, block 27 of elements of sum modulo two, delay element 28, second 29, fifth 30 and fourth 31 elements OR, AND-NOT element 32, first 33 and second 34 elements NOT, third 35, eighth 36, sixth 37 and seventh 38 elements OR, third 39, second 40, seventh 41, eighth 42, fourth 43 , fifth 44, sixth 45 and first 46 elements I.

FIG. 1 also indicates device information input 47, device logical conditions input 48, device installation input 49, third 50 and quarter 51 device control inputs, first 52 and second 53 device control inputs, first stack memory control input 54, information input stack 55 of the stack memory, clock input 56 of the stack storage unit, second control input 57 of the stack storage unit, first control output 38 of the stack storage unit, first information output 59 of the stack storage unit, second control output 60 bl Open stack memory, the second information output 61 of the stitch memory block, the first 62 and the second 63 control outputs of the device.

Block 3 of the stack memory (Fig. 2) contains blocks 64.1-64.p of registers (where n is the depth of the stack of the first 65 and second 66 switches.:

The operation of the device begins by applying the initial setup signal to input 49. The initial setup pulse through the OR element 31 enters the R-inputs of register 5 of logic conditions, counters 9 and 10 of stack depth, counter 8 of the length of a linear sequence of nano commands, register 6 of an address, trigger 17 trigger, synchronization counter 11 and through the OR element 30 Ha.R-inputs of the first 15 and second triggers 16 fixing the label, through the OR element 29 to the R-input of the register of 4 commands, through the OR elements 37 and 38 of the first 18 and second 19 triggers control trigger 20 is set Application

When a command is received that determines the address of the program for the formation of control commands, the command, via the SHSh 24 on

The output of the one-shot 22 generates a pulse. This impulse arrives at the synchronization input of the register of 4 commands, thereby ensuring that the code is written from the input 47 of the device to the register of 4 commands. "

Simultaneously with the recording of information in the register of 4 commands, a pulse at the output of the one-shot 22 sets the trigger trigger 17 to one state. The logic level from the trigger trigger 17 output allows the generation of clock pulses at the output of the generator 21 for synchronizing the operation of the devices. The pulses from the output of the generator 2 through the element And 46 is fed to the input of the counter 11 synchronization. The passage of clock pulses through AND 46 is due to the fact that the 8-dpi counter of a linear sequence of nano-commands is in the zero state and therefore the output of the HE element is 32 states of a logical unit.

When the state of the synchronization counter II changes, a logic one signal appears at the first output of the synchronization decoder 14. This signal provides a leading edge overwriting information from the register of 4 commands through the block of elements OR 23 to the register 6 of the address. The next pulse of the oscillator 21 results in a change in the state of the synchronization decoder 14. The impulse from the second output of the decoder 14 is fed to the synchronization inputs of counters 7 and 8, thereby ensuring the recording of information from the corresponding fields of the block 1 of the address memory into these counters. In addition, the same pulse through the element OR 29 sets to zero the register of 4 commands.

The entry of a code into the counter of 8 dpins of a linear sequence of nano-commands results in the appearance of a logical zero level at the output of the AND-NOT 32 element. This prohibits the passage of generator pulses 21 through the AND 46 to the input of the synchronization counter 11. At the same time, the level of a logical unit appears at the output of the element HE 33, which allows the passage of synchronization pulses from the output of the generator 21 through the element 40. At the third input of the element 40 there will be a signal of the logical unit. This is because the counters 9 and 10 of the stack depth are in the zero 14957-466

The information in address register 6 is formed from the following sequence number code from field 11 of memory block 1, supplemented (depending on the progress of the control process) with information from register 5 of logical conditions. The variable part of the address is formed by modifying on block 27 the elements of the sum modulo two information of the register 5 by logical conditions coming from the input 48 of the device. The following operation cycle is repeated.

. At any given time, a command to stop one of the two running processes will be submitted. When stopping the advancement of the first process, a pulse is applied to the input 50 of the device. (FIG. 2) of block 3 of stack memory. These 20 This impulse translates the trigger 18 of the operation. Consequently, at the first outputs of the decoders 12 and 13, the depth of the stack will be a logical unit. Since the first codes of the decoders 12 and 13 are not connected to the inputs of the elements OR 25 and 26, then the output of the element And 41 will be a signal of logical zero. This signal is fed to the input element HE 34 and allows the passage of clock pulses through the element 40 from the output of the generator 21.

The synchronization pulses from the output of the AND 40 element arrive at the summing input of the counter 7 of the address, thereby providing a sequential reading from the memory block 2.

The memory of the nano-command read from block 2 is fed to input 55

ten

The nano commands from the outlets 59 and 61 of the stack memory unit 3 are fed to the outlets 62 and 63 of the device (Fig. 1) for control of the executive elements and blocks.

At the same time, the sync pulses from the output of the AND 40 element are fed to the subtracting input of the counter 8 of the length of the linear sequence of nano commands. When the counter 8 reaches the zero state, a signal of a logical unit appears at the output of the NAND 32 element. This signal through the element And 46 allows the passage of pulses sichroniza-. Qing from the output of the generator 21 to the input of the synchronization counter 11 At the same time, at the output of the element HE 33 a logical zero signal appears, which prohibits the passage of synchronization pulses from the output of the generator 21 through the element 40.

The next pulse from the output of the generator 21 changes the state of the synchronization counter 11, which, in turn, causes the occurrence of a pulse at the third output of the decoder 14 of the synchronization. This pulse through the IRZ element 35 sets the address 7 to zero. At the next synchronization pulse, a pulse appears at the fourth output of the synchronization decoder 14, which ensures the recording of information into the register 5 of logical conditions from the corresponding field of the block 1 of the address memory.

The next sync pulse causes the appearance at the first output of the torus 14 of a pulse, which ensures the recording of information in the address register 6.

35

in a single state. The logical zero signal from the inverse output of the trigger 18 inhibits the operation of the decoder 12 of the depth of the window. This causes the prohibition of the passage of nano-commands to the output 62 of the device through the block 3 of the stack memory. The signal of the logical unit from the direct output of the control trigger 18 allows the synchronization pulses to pass through the elements 40 and 43 to the summing input of the stack depth counter 9, which determines the delay value of issuing control commands of the first process. At the same time, the level of the logical unit from the direct output of the control trigger 18 through the OR element 36 sets the setup trigger 20 to the one state. It provides

4Q passing the synchronization pulses through the element 45 and the element 28 of the entry delay 56 of the stack memory unit 3. The incoming sync pulses produce a consistent

The nano commands in the stack memory consist of a block of registers 64.1-64.p, where n is the depth of the stack (Fig. 2).

To restart (restart) the delayed first process from input 52

50, a logical unit signal is applied. By this signal, through the OR element 37, the control trigger 18 goes to the zero state. Logical unit level with inverse

its output of the trigger 18 control permits the operation of the decoder 12 of the stack depth, which at the input 54 of the stack memory unit 3 permits the matching of the nano commands from the corresponding register

ten

five

in a single state. The logical zero signal from the inverse output of the trigger 18 inhibits the operation of the decoder 12 of the depth of glass. This causes the prohibition of the passage of nano-commands to the output 62 of the device through the block 3 of the stack memory. The signal of the logical unit from the direct output of the control trigger 18 allows the synchronization pulses to pass through the elements 40 and 43 to the summing input of the stack depth counter 9, which determines the delay value of issuing control commands of the first process. At the same time, the level of the logical unit from the direct output of the control trigger 18 through the OR element 36 sets the setup trigger 20 to the one state. It provides

Q is the passage of synchronization pulses through the element 45 and the element 28 of the input delay 56 of the stack memory unit 3. The incoming sync pulses produce a consistent

putting nano commands into a stack memory consisting of a block of registers 64.1-64.p, where n is the depth of the stack (Fig. 2).

To restart (restart) the delayed first process from input 52

0, a logical unit signal is applied. By this signal, through the OR element 37, the control trigger 18 goes to the zero state. Logical unit level with inverse

The output of the trigger 18 of the control permits the operation of the decoder 12 of the stack depth, which, at the input 54 of the block 3 of the stack memory, allows the matching of nano commands from the corresponding register

71495746

the block of registers 64.1-64 n through the switch 65 to the output of the device 62. The logical zero level from the direct output of the control trigger 18 prohibits the passage of synchronization pulses through the AND 43 element to the summing input of the stack depth counter 9. As a result, the first process control commands are issued with a delay of to to a specified number of clock cycles relative to the second process.

To stop the progress of the second process, a logical unit signal is applied from the device input 51. By this signal 15, the control trigger 19 goes into one state. The logical zero level from the inverted output of the control trigger 19 prohibits the operation of the decoder 13 of the depth 20 of the stack. This prohibits the passage of nanocommands to control the second process at output 63 of the device.

The level of the logical unit from the output of the trigger trigger 19 of the control 25 permits the passage of synchronization pulses through the element 44 to the summing input 10 of the stack depth. However, if the first process does not

Signal logical e; The pins from the output of the element I enter the input of the element NOT 34. The logical zero signal generated at the output of the element 34 does not allow the synchronization pulses to pass through the element 40. As a result, the counter 7 of the address stops, the counter.8 the length of the linear sequence of nanocands stops recording information into the block of registers 64.1-64.p of block 3 of the stack memory. At the same time, the level of the logical unit from the output of the AND 41 element allows the passage of clock pulses from the output of the generator 21 through the AND 42 element to the subtractive inputs of the first 9 and second 10 stack depth meters. The subtraction occurs until one of the counters goes to zero state the At the same time, the information on outputs 62 and 63 does not stop.

Since the outputs of the decoders 12 and 13 of the stack depth, the corresponding

was delayed, then through the OR element 36 30 to the standing of the counters 9 and 10 of the depth, the trigger 20 is set to remove the copy in the unit state. For restarting the delayed second process, from the input-53 device is fed

a single signal that translates the trigger 5 to the zero state appears to control the control to zero. In this case, the operation of the descrambler 13 of the stack depth is enabled and the passage of sync pulses is prohibited. from element I 44 to the summing input of counter 10 of the stack depth. Thus, the command is read.

the logical zero. As a result of this, the operation of the address counter 7 is restored, the counter 8 of the length of the linear sequence of nano-commands restores the recording of information into the block of registers 64..n the block 3 of the stack memory.

50

through the appropriate register of the block of registers .p of block 3 of the stack memory (Fig. 2) through the switch 66 j to the input 63 of the device.

In that case, if the delay was made, the output of one of the two generated processes, and then the other, i.e. There should be a copy of both processors; with a given delay of one relative to another, the device works as follows.

From the outputs of the decoder 12 stack depth code arrives at the element OR 25, resulting in the first input of the element And 41 will be the level of a logical unit. At the same time, the code from the outputs

55

eight

The decoder 13 of 1 stack goes to the element OR 26, which causes the appearance of the level of the logical unit on the second input of the And 41 element.

Signal logical e; The pins from the output of the element I enter the input of the element NOT 34. The logical zero signal generated at the output of the element 34 does not allow the synchronization pulses to pass through the element 40. As a result, the counter 7 of the address stops, the counter.8 the length of the linear sequence of nanocands stops recording information into the block of registers 64.1-64.p of block 3 of the stack memory. At the same time, the level of the logical unit from the output of the AND 41 element allows the passage of clock pulses from the output of the generator 2 through the AND 42 element to the subtracting inputs of the first 9 and second 10 counters of the stack depth. The subtraction occurs until one of the counters goes to zero state the At the same time, the information on outputs 62 and 63 does not stop.

Since the outputs of the decoders 12 and 13 of the stack depth, the corresponding

ka, are not connected to the inputs of the corresponding elements OR 25 and 26, then at the output of the Element ШШ 25 (26), corresponding to the stack depth counter with

zero state appears

the logical zero. As a result, the operation of the counter 7 of the address, the counter 8 of the length of the linear sequence of nano commands is restored, the recording of information in the block of registers 64 is restored. In block 3 of the stack memory.

Thus, the delay of the processes relative to the initial value and between themselves is maintained. At the same time, the stack depth counters are in the state of the lowest possible filling.

The end of the device is as follows.

 - a sign of the end of the process on outputs 58 and 60 of the block 3 of the stack memory, depending on the ratio of the delay between processes, alternately triggers the fixation of the label 15 and 16 into a single state. The level of the logical unit from the output of the element AND 39 through the element OR 31 sets the memory elements of the device to the initial (zero) state. A device for software control of technological processes is ready to form and issue the next set of control commands.

If in the period between the labels on one and another process comes. If the next command is sent to the device input 47, then the trigger fixes 15 and 16 are set to the zero state through the OR element 30 from the pulse at the output of the one-shot 22. In this case, the device continues to work in the same way as before.

Thus, the device for software control of technological processes allows to dynamically produce stopping and advancing processes, which expands its functionality and, consequently, the field of expedient application.

In the case of sequential organization of the formation of control commands, there is poor performance, due to the large losses of time waiting for the end of the issuance of the control subroutine and the impossibility of issuing commands in parallel across several KIM channels. This disadvantage reduces the functionality of the device and, as a result, limits its scope.

For example, to form two identical control subroutines, time will be required, determined by the expression

T, (P,) 2 TO,

where Tp is the formation time of one.

subprograms (P, P), and

- (P,) - 1 (P,) TO, (1),

where i (ПЛ-СС П) is the moment when control commands are issued.

Thus, the discipline of forming two identical subprograms

The expressions for which expression (1) is valid, the time delay is determined by the following expression

LT, TO - L (P ,, P,) TO -

- t cnj (n

The control program P, (P) can also be understood as a group (core; sequentially) formed. identical fragments of control commands

g / g

where

ПДП,) - п; (г7р, п; (п,),., г7, (п),

V, el, p: P P pi, f, l (P, P,.,) 0.

Then the formation time of the control program is defined by the expression

1C

 2 I. T ,,,

1-1

where is TO; - subprogram formation time.

. The time delay of LT, the issuance of subroutines can be estimated by the formula

LT, e | -T „. -I (P;, P-,)

In this case, the loss of production, these devices are determined by the expression

25 30

35

40

five

Q

five

UY

t, s (n; .p;)

pp

Thus, the known technical performance with respect to the proposed device for software control has a comparatively low productivity and, therefore, a field of application.

A device for software control of technological processes can find application in programmable controllers, computers in the control of identical processes, automatic control systems.

Claims (1)

Invention Formula The device dp software process control, which contains the address memory, memory, address register, command register, logical condition register, synchronization counter, OR block, start trigger, clock generator, two AND, you-, first element I is connected to the counting input of the synchronization counter, the output of the command register is connected with the first input of the OR block whose output is connected to the information input of the address register, the output of the address register is connected to the input of the address memory block, the first output of the address bit field of which is connected to the second input of the OR block, the second output of the address memory block is connected with the information input of the logical conditions register, the direct output of the trigger trigger is connected to the control input of the clock generator, characterized in that, in order to expand the field of application based on the implementation of dynamic stop and advance processes, the device has an address counter, an absolute modulus of two sum elements, a sequence length counter of nano commands, a single-oscillator, an AND element — NOT, two NE ems, a synchronization decoder, the first and second stack depth counters, two stack depth decoders, nine OR elements, stackable memory block, installation trigger, two mark firing triggers, two control triggers, six AND elements, a delay element, the information input of the device is connected to the information input of the command register and to the input of the first / OR element whose output is connected with the input of the one-shot, the output of which is connected to the S-input of the trigger trigger, the output of the clock pulse generator is connected to the first inputs of the first and second elements And, the output of the first element And is connected to the synchronizing input of the decoder nhro nizara, the input of which is connected to the output of the synchronization counter, the output of the register of logical conditions is connected to the first input of the sum modulo two element block, the input of the logical conditions of the device is connected to the second input of the block of sum total modulo two, the output of which is connected to the information input of the address register The output of the address floor of the nano-command of the memory block of addresses is connected to the information input of the address counter, the output of which is connected to the input of the memory block. The output of the field of the number of nano-commands of the memory block of the addresses is connected to n-formational input of the counter of the sequence length of nano-commands, the zero outputs of which are connected to the inputs of the element AND-NOT, the output of which connected to the second input of the first element I and to the input of the element NOT whose output is connected to the second input of the second I element, the output of the second element I connected to the summing input of the address counter whose output is connected to the input of the memory block, the first output of the synchronization depressor the synchronization input of the address register, the second output of the synchronization decoder is connected to the synchronization inputs of the nanocommand linear distribution length counter, the address counter and the first input of the second OR element, the output of which o is connected to the R-input of the command register, the third output of the sync synchronization decoder is connected to the first input of the third OR element, the output of which is connected to the R-input of the address counter, the quarter output of the synchronization decoder is connected to the synchronization input of the logical conditions register, the output of the second And element is connected to the subtractive input of the linear sequence length sequence of nanocands and the summing input of the address counter, the one-shot output is connected to the command register synchronization input, the output of the memory block is connected to the inform The primary input of the stack memory unit, the first and second information outputs of which are connected respectively to the first and second control outputs of the device, the first and second control outputs of the stack memory unit are connected to the S inputs of the first and second label fixation triggers, respectively. Wee outputs of which are connected respectively to the first and second inputs of the third element AND, the output of which is connected to the first input of the fourth element OR, the second input of which is connected to the installation input of the device, output h The third OR element is connected to the first input of the fifth OR element, the second input of the second OR element, the R-input of the address register, the R-inputs of the logical conditions register, the first and second stack depth counters, the linear sequence length of micro-instructions, the synchronization counter, the R-input trigger trigger, the second input of the third OR element, the first inputs of the sixth and seventh OR elements and the R input of the setup trigger, the first and second the control inputs of the device are connected to the second inputs of the sixth and seventh OR elements respectively, the outputs of which are connected to the R inputs of the first and second control triggers respectively, the third and fourth control inputs of the device are connected to the S inputs of the first and second control triggers, respectively the one-shot output is connected to the second input of the fifth RSH element, the output of which is connected to the R inputs of the first and second tag-latching trigger; the direct output of the first control trigger is connected to the first input of the second of the fourth OR element and the first input of the fourth AND element, the output of which is connected to the summing input of the first counter of the main stack, the output of the second element AND is connected to the second output of the fourth AND element, the first input of the fifth And element and the first input of the sixth And element, the fifth output element AND is connected to the summing input of the second stack depth counter, the direct output of the second control trigger is connected to the second V5SODOM of the fifth element AND and the second input of the eighth OR element, the output of which is connected to the S-input of the remove trigger opium, a direct output which is connected to the second input of the sixth And element, the outputs of the first and second stack depth counters are connected to the inputs of the first and second stack depth decoders, respectively, the control inputs of which are connected to the inverse outputs of the first and second triggers, respectively control, the output of the sixth And element - through the delay element connected to the clock input of the stack memory block, the output of the first depth decoder The stack is connected to the input of the ninth OR element and the first control input of the stack memory block, the output of the second decoder of the stack depth is connected to the input of the dec of the OR element and the second control input of the stack unit memory, the outputs of the first and second decoders of the stack stack are connected respectively to the first one (And the second outputs of the seventh. And, whose output is connected to the first input of the eighth And element and the second element input, the output of the clock generator is connected to the second input of the eighth And element The output of which is connected to the subtractive inputs of the first th and second stack depth counters, the output element is NOT connected to the third input of the second element I. FI.2