SU1494204A2 - Digital frequency-phase discriminator - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to reduce the transition time to the phase comparison mode from the frequency comparison mode. The discriminator contains a counter 1, a static register 4, a block of prohibition 6, an element EXCLUSIVE OR 7, D - triggers 8 and 9, shapers 10 and 19 short pulses, elements OR 11, AND 12, AND-NOT 13-70, 20 and 21 and Inverter 18. From the frequency comparison mode, the discriminator enters the phase comparison mode and the synchronism mode is set. Turning off the frequency comparison mode occurs after changing the sign of the frequency difference between the input and reference signals, when the phase difference of these signals begins to decrease from cycle to cycle in the direction from 2ϕ to 0. Passing the phase difference of input signals through ϕ / 2 reduces the transition time to the comparison mode phases from the frequency comparison mode. 3 il.

Description

The invention relates to radio engineering and can be used in phase locked loop systems.

The purpose of the invention is to reduce the transition time to the phase comparison mode from the frequency comparison mode.

FIG. Figure 1 shows a structural electrical circuit of a digital frequency-phase discriminator; in fig. 2 and 3 are time diagrams for his work.

The digital frequency-phase discriminator (DSPD) contains counter 1, input 2 of counting pulses, input 3 reference pulses, static register 4, signal input 5, block 6 of the prohibition, element ORIGINAL OR 7, first 8 and second 9 D-triggers, first driver 10 short pulses, the element OR 11, the element And the 1st Fifth 13, the fourth 14, the third 15, the second 16 and the first 17 elements AND-NOT the inverter 18, the second shaper 19 short pulses and the sixth 20 and the seventh 21 elements AND-NOT 20, 21.

Digital frequency-phase discriminator works as follows.

The reference pulses from input 3 to the installation O of counter 1, at the outputs of the latter, are set O. The counting input T of counter 1 is connected to input 2 of the counting pulses. The frequency of the counting pulses is determined by the expression:

sch

N

where 2

-1 is the capacity of the counter 1, T is the period of the reference impulses.

In the MOM.JHT of the arrival at the input 5 of the input pulse at the input of the static register 4, information from counter 1 is written into the static register 4, thus forming a binary code at the output of this register} 1a, whose value N is proportional to the phase difference of the input and reference pulses.

If the frequency of input pulses arriving at input 5 is greater than the frequency of the reference pulses arriving at input 3 (f J, 7 f of,), then the phase difference of these signals decreases from cycle to cycle in the direction from 2 ff to O, simultaneously decreases and magnitude of two

0

five

0

five

0

five

0

five

an alternative code N at the output of the frequency frequency-phase discriminator (Fig. 2a).

When the phase difference between the input and reference signals reaches at time t, O, and the binary code at the output of the digital frequency-phase discriminator reaches a jump-like change in the phase difference of the input signals from O to 2, and the binary code reaches N pp. „Px At the same time, the (bit + 1) -ro sign bit of the static register 4 from O to 1 (Fig. 2b) is switched, with which 1 is recorded from the output of the EXCEL SCHEEE OR 7 (Fig. 2c) element to the first D -trigger 8. At the direct output of this D-flip-flop, 1 appears (Fig. 2d), and at the inverse - O, which causes the appearance of 1 at the output of the second element AND-NOT 16 (Fig. 2e), i.e. . in the most significant bit of the output code of the digital frequency-phase discriminator. This 1 switch off the least significant bits of the output of the CPCFD code, received through the prohibition block 6, and also causes the appearance of 1 at the output of the element OR 11. At the output of the first element

AND-NOT 17, i.e. in the sign of the output of the CPCFD code, O will be set (FIG. 2e). CCPD goes into frequency comparison mode with the sign O, while the fourth 14 and sixth 20 elements AND-NOT are closed with the zero level of the direct output of the second U-flip-flop 9 (Fig. 2g), and the fifth 13 and the seventh 21 elements AND-NOT are open unit level of the direct output of the first D-flip-flop 8 (Fig. 2d).

In the mode of comparing the frequencies t,; t t 3 decreases the rate of change of the binary code at the output of the static register 4 (dotted line in Fig. 2a), and therefore the rate of change of the phase difference of the input and reference signals decreases. At the transition of the phase difference between the input and reference signals of the value at the moment ti, switching from 1 to O of the output level of the EXCLUSIVE OR 7 element (Fig. 2c) and a pulse from the output of the first shaper 10 short pulses (Fig. 2h) working on the negative front occurs at the inputs of the fourth 14 and p of the 13 elements NAND. The coincidence of short pulses of the first forkirovator 10 (Fig. 2h) with negative pulses of the inverse (k + 1) -ro sign bit of the static register 4 (Fig. 2i) at the input of the fifth AND-HE element 13 and with the zero level of the second D-trigger 9 at the input of the fourth item, AND-NO 14, prevents the frequency comparison mode from being turned off. When the frequency detuning decreases, the rate of change of the phase difference between the input and reference signals decreases and becomes zero at time t 3, after which the sign of the frequency difference changes and the phase difference between the input and reference signals begins to increase from cycle to cycle in the direction from O to 2 ff and when switching over 3lf / 2 at time t4, switching from O to 1 of the output level of the EXCLUSIVE OR 7 element (Fig. 2c) and switching from 1 to O of the output level of the inverter 18 occurs, which ultimately leads to reduction of the transition time phase matching from the frequency comparison mode. The negative front of the output voltage of the inverter 18 triggers the second pulse shaper 19 (Fig. 2k), the output pulse of which is fed to the inputs of the seventh 21 and sixth 20 I-NOT elements. The sixth element AND-NOT 20 is closed by zero levels coming from the inverse (k + 1) -ro sign bit of the static register 4 (Fig. 2i) and from the direct output of the second D-flip-flop 9 (Fig. 2g). The coincidence of the output pulse of the second shaper 19 short pulses at time t with a positive pulse coming from the output of the (k + 1) -ro sign bit of the static register 4 (Fig. 2b) causes the appearance at the inputs of the open seventh IS-NOT 21 element a negative pulse at the output of the seventh element AND-HE 21, which, through the element 12, goes to the R-inputs of the first and second D-flip-flops 8 and 9, reset the first D-flip-flop 8 and turn off the frequency comparison mode. The CCPP switches to phase comparison mode and sets the synchronism mode.

If the frequency of input pulses arriving at input 5 is less than hour0

five

0

five

0

the reference pulses arriving at input 3 () then the phase difference of these signals increases from cycle to cycle in the direction from O to 21, and the value of the binary code N at the output of the CPPD increases at the same time (Fig. 3a). When the phase difference between the input and reference signals reaches 21f at time t, and the binary code at the output of the CSFD reaches the value Nnp, dcpp, a stepwise change in the phase difference of the input signals from 2 ff to O

5 and the value of the binary code - to

. .At the same time, the inverse (k + 1) -ro sign bit is switched from O to 1 (Fig. 3i), with the help of which

Q record 1 from the output of the element ORIGINAL OR 7 (fig. Sv) in the second D-flip-flop 9 and at its direct output appears 1 (fig. Zj), and in the inverse - O, which causes appearance 1 on the output of the second element AND-NOT 16 (Fig. Zd) and the output of the first element AND-NOT 17 (Fig. Ze). The CCPF enters the frequency comparison mode with the sign 1, with the Fifth 13 and the Seventh 21 AND-NOT elements being closed with the zero level of the direct output of the first D-flip-flop 8 (Fig. Zg), and the fourth 14 and the Sixth 20 AND-NOT elements are open unit level of the direct output of the second D-flip-flop 9 (Fig. Зж).

The coincidence of short pulses of the first driver 10 (Fig. 3) with negative pulses () -ro sign bit static register 4 (Fig. 36) at the input of the fourth element IS-HE 14 and with the zero level of the first D-flip-flop 8 at the fifth input element NAND 13 prevents the comparison mode from being turned off, frequencies. I.

Turning off the frequency comparison mode occurs after changing the sign of the frequency difference between the input and reference signals, when the phase difference of these signals starts to decrease from cycle to cycle in the direction from 21Г to O and when going through / 2 (which results after passing the phase difference of the input signals through and / 2 to the reduction of the transition time to the phase comparison mode from the frequency comparison mode) at time 14 the output pulse of the second generator 5

0

five

l 19 (Fig. G3) coincides with the positive pulse of the inverse (k + 1) -r sign bit of the static register 4 (fig. Zi) at the inputs of the open sixth element AND-HE 20. At the output of the sixth element AND-HE 20 a negative impulse appears, which, through element 12, acting on the N-inputs of the first and second D-flip-flops 8 and 9, sets the second D-flip-flop 9 to O.

Thus, the transition to the phase comparison mode occurs not only when the input signal pulses intersect the O and 2 f values of the phase characteristic, but also when the values intersect if the frequency difference change sign was preceded by the frequency comparison mode f op 311/2, if the frequency difference sign changed preceded by the mode of comparing the frequencies f ix opV of both cases, the transition to the mode of comparing the phases of the proposed discriminator is faster than in the prototype (dash-dotted line in Fig. 2a and Za at tt)

In addition, the proposed discriminator has a high noise immunity when the input signal fades, since when the pulses at input 5 are lost in synchronism mode, the static register 4 stores information about the phase difference between the input and reference pulses

shems mode. Under these conditions, the discriminator remains in phase comparison mode.

The use of the invention makes it possible to reduce the duration and magnitude of the transient overshoot and, consequently, increase the speed of the frequency-phase-locked loop systems.

Claims (1)

Invention Formula Digital frequency-phase discriminator auth.St. No. 1390774, which is characterized by the fact that, in order to reduce the transition time to the phase comparison mode from the frequency comparison mode, the sixth and seventh AND –NE elements, the inverter connected in series and the second short pulse shaper are additionally entered into it connected to the output of the EXCLUSIVE OR element, and the output of the second short pulse shaper - with the first inputs of the sixth and seventh AND-NES elements, the second inputs of which are connected to the C inputs of the second and first D-flip-flops, respectively, and the third inputs of the Comm Nena with straight outputs the second and first D-flip-flops, respectively, wherein the outputs of the sixth and s.edmogo AND-NO elements are connected to the fourth and fifth inputs of the AND respectively. Affffy. tvzh / V . fna.