SU1624675A1 - Device for pulse deletion and insertion - Google Patents

Abstract

The invention relates to automation and computing and can be used in phase-locked loop circuits and in phase converters for controlling drives of robots or machine tools. The device for subtracting and adding pulses contains a frequency divider 1, triggers 2-4, elements AND 5 and 6, element OR 7, bus 8 reference pulses, control bus 9, bus 10 corrective pulses, exit bus 11. Eliminating the possibility of distortion of the pulse sequence by the output bus, in the event of the appearance of impulsive noise on the control bus, improves the noise immunity of the device. 2 sludge.

Description

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The invention relates to automation and computing and can be used in phase-locked circuits and in phase converters for controlling drives of robots or machine tools.

The purpose of the invention is to improve the noise immunity of the device by eliminating the possibility of distortion of the pulse sequence on the output bus in the event of a pulse of interference on the control bus.

FIG. Figure 1 shows the electrical structure of the device; in fig. 2 - timing diagrams for the operation of the device.

The device (Fig. 1) contains a frequency divider 1, the input of which is connected to the C input of the first trigger 2, and the output to the C inputs of the second 3 and third 4 trigger. The input and output of the divider 1 is connected to the first inputs of the first 5 and second 6 AND elements, respectively, the outputs of which are connected respectively to the first and second inputs of the element OR 7. The input of the divider 1 is connected to the bus 8 of reference pulses, the D-input of the trigger 2 bus 9 control, S-trigger input 3rd bus 10 corrective pulses, the output of the element OR 7 - with the output bus 11. The output of the trigger 2 is connected to the second input of the element 5, the third input of which is connected to the inverse output of the trigger 4, the direct output of which is connected with the second input element And 6. D-in Trigger 3 is connected to the logic potential O bus, and the output is connected to the D-input of trigger 4.

The device works as follows.

The reference pulse sequence arrives at the input of the divider 1 (Fig. 2a). As a splitter 1, a pulse distributor can be used, which uses one of its outputs. Using pulses from the output of divider 1 (Fig. 26), trigger 3 is set to state O at the forward output, since the D input of trigger 3 is connected to the potential O bus. If bus 10 of corrective pulses has no pulses (input signal O) , the trigger 4 pulses from the output of the divider 1 is set to the state corresponding to O on the forward output, which prevents the pulses from the output of divider 1 through the AND 6 element. If the O signal is present on the control bus 9, the AND 5 element is closed by the signal with direct output trigger 2, which prep It supports the passage of the reference pulse sequence on the bus 11 of the device.

Thus, the presence of signals O on tires 9 and 10 corresponds to the absence of pulses on the bus 11 of the device.

When a pulse appears on bus 10 (Fig. 2d), trigger 3 is switched to the state corresponding to the direct output (Fig. 2e). The impulse from the output of the divider 1 switches the trigger 4 to the state 1 on the direct output (Fig. 2e). In this case, the passage of the pulse sequence from the output of the divider 1 through the element 6 (fig. 2g) and further to the bus 11 of the device through the element OR 7 is allowed. The passing of the reference pulse sequence through AND 5 is also prohibited by the signal from the inverse output of the trigger 4.

Another limiting case corresponds to the presence of signal 1 on bus 9 (Fig. 2c) and the absence of corrective pulses on bus 10. In this case, the forward output of flip-flop 2 and the inverse output of flip-flop 4 generate signals 1 permitting the passage of the reference pulse sequence (FIG. 2a) through the element AND 5 (FIG. 2h) and further through the element OR 7 (FIG. 2i) onto the bus 11 of the device. In this case, the signal O from the direct output of the trigger 4 closes the element 6.

To prevent skip corrective pulses, trigger 3, in contrast to triggers 2 and 4, is switched on the trailing edge of the reference pulse (Fig. 2e).

Thus, on the device bus 11, limit pulse sequences can be obtained from the complete absence of pulses to the reference sequence. It is possible to obtain intermediate values of pulse signals.

In the event of a pulse noise on bus 9 (Fig. 2c), the operation of the device is not impaired.

Claims (1)

The invention is a device for subtracting and adding pulses, containing the first and second elements AND, the outputs of which are connected respectively to the first and second inputs of the OR element, the output of which is connected to the output bus, from the first to the third triggers, the frequency divider, the input is connected to the reference bus pulses, and the output with the first input of the second element And and the C-stroke of the third trigger, the D-loop of which is connected to the output of the second trigger, and the control bus is connected to the output of the second trigger, as well as the control bus and bus correction pulses, characterized in that, in order to increase the noise immunity of the device by eliminating the possibility of distortion of the pulse sequence on the output bus in the event of pulse interference on the control bus, the first input of the first element I is connected to the reference pulse bus and the C input of the first trigger, The D input of which is connected to the control bus, and the output to the second input of the first element four ppppppppp rf pppppppg And, the third input of which is connected to the inverse output of the third trigger, the direct input of which is connected to the second input of the second element I, the first pass of which is connected to the C input of the second trigger. S is the input of which is connected to the bus of correction pulses, and the D input is connected to the bus of logic O.