GB2235103A - Programmable square wave generator - Google Patents

Programmable square wave generator Download PDF

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Publication number
GB2235103A
GB2235103A GB9018147A GB9018147A GB2235103A GB 2235103 A GB2235103 A GB 2235103A GB 9018147 A GB9018147 A GB 9018147A GB 9018147 A GB9018147 A GB 9018147A GB 2235103 A GB2235103 A GB 2235103A
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United Kingdom
Prior art keywords
counter
pulse width
value
output
square wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9018147A
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GB9018147D0 (en
Inventor
Dong-Soo Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Goldstar Electron Co Ltd
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Filing date
Publication date
Application filed by Goldstar Electron Co Ltd filed Critical Goldstar Electron Co Ltd
Publication of GB9018147D0 publication Critical patent/GB9018147D0/en
Publication of GB2235103A publication Critical patent/GB2235103A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
    • H03K3/72—Generators producing trains of pulses, i.e. finite sequences of pulses with means for varying repetition rate of trains

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

In a programmable square wave generator equipped for example in a microcomputer unit, the period of the square wave and the duty cycle can be controlled by a program which compares the value of a pulse width register with the value of a counter. This programmable square wave generator comprises: two pulse width registers 1, 5 for recording the pulse width data, a counter 3, two comparative circuits 2, 4, a pulse generator 6 and a data bus 7. Signals EQI and EQII are produced when the respective comparative circuits indicate agreement and under opposite conditions of the output of the pulse generator. <IMAGE>

Description

55809.308 Programmable scruare wave qenerator This invention relates to a
programmable square wave generator, more particularly, to a programmable square wave generator that may be provided in a microcomputer unit, in which the period of the square wave and the duty cycle can be controlled by a program.
A timer counter having a reload function has been used in known square wave generating circuits for single chip microcomputers. The operating method of this conventional timer counter is that the initial value of the timer counter is set by the microprocessor, and then, the value becomes zero by counting down the clock input of the timer counter, and at this time the periodic signal is output by switching a flip-flop. With such a counter, the period can be variable but the duty cycle is fixed to 50%.
Another timer counter which can vary the duty cycle has also been known. The operating method is that the output is set at the time when the timer load register value agrees with the timer counter value, and the output is reset at the time when the timer counter overflows. With this counter, the duty cycle is variable in a fixed period, or the duty cycle can be variable when the timer counter has an autoreload function, but only a pulse having a fixed duty cycle can be output.
Summary of the Invention
The object of the invention is to provide a programmable square wave generator equipped in a microcomputer unit, in which the period of the square wave and the duty cycle can be controlled by a program, which compares a value in a pulse width register with the value of a counter. This programmable square wave generator comprises two pulse width registers for - 2 storing the pulse width values, a counter, a first comparator connected to a first one of said pulse width data registers and to said counter, for comparing the value of said first pulse width data register with the value of said counter, a second comparator connected to the second pulse width data register and to said counter, for comparing the value of said second pulse width data register with the value of said counter, and a pulse generator connected to said first and second comparators, whereby said pulse generator outputs a signal of a first level until the counter is equal to a value stored in said first pulse width data register and then outputs a signal of a second level until the counter is equal to a value stored in said second pulse width data register, thereby providing a square wave in which the period of the square wave and the duty cycle can be controlled by a program. This arrangement allows a programmable square wave generator to be provided which allows both period and duty cycle to be controlled, whilst employing only a single counter.
An embodiment of the invention will now be described by way of example only and with reference to the accompanying drawings.
Brief DescriDtion of the Drawinqs Fig. 1 Shows a block diagram of a programmable 30 square wave generator according to th s invention. Fig. 2 Shows an output waveform of the apparatus of Fig. 1. Fig. 3 Shows an example of a counter input wave.
Fig. 4 Shows one example of a system clock wave.
Fig. 5 Shows a pulse generator and a control circuit of the apparatus.
1 1 1 Fig. 6 - 1 Shows a counter circuit stage of the apparatus.
Fig. 6 - 2 Shows an enlarged internal circuit of the CNR1 part of the counter circuit.
Fig. 7 - 1 Shows a comparative circuit stage of the apparatus.
Fig. 7 - 2 Shows an enlarged internal circuit of an ND, part of the comparative circuit.
Fig. 8 Shows a timing diagram.
Fig. 9 Shows an operation flow chart of the apparatus.
As shown in Fig..1, a programmable square wave generator comprises a first pulse width data register is (1), a first comparative circuit or comparator (2), a counter (3), a second comparative circuit (4), a second pulse width data register (5), a pulse generator (6) and a data bus (7). Hereinafter, we explain the structures and the functions of this programmable square wave generator on the supposition that it is provided as a peripheral component of a microcomputer unit. The central processing unit (CPU) of the microcomputer records the data to determine the low level width of the square wave in the first pulse width register (1) and the data to determine the high level width of the square wave in the second pulse width register (5).
If the CPU enables the counter (3), the counter starts to count up by receiving the input clock. Referring to Fig. 6-1, the operating mechanism of the counter (3) can be explained on condition that the input clock is the same waveform as shown in Fig. 3. The initial input clock is applied to 5- Fi-i(i=0) of the first stage of the counter. The initial states of each part of said counter are set as follows: CLR is set to be High, the output of WR1 is Low, the output of N4 'S High, the output of CN 4 is Low, the output of N5 is High, the output of NR2 is Low and the output of N3 is High.
From this initial state, CLR becomes Low and the counter begins to operate. If the input clock is High, the output of NR2 remains Low. Since the input of CNRi NOR gate at the AND side is high when the clock and output of N5 are High, the output of CNR1 remains Low when the system clock 2 (02) is High. If the input clock becomes Low, the output of NR2 remains Low without any change.
But the output of CNR1 becomes High when the AND input of CNR1 NOR gate becomes Low and system clock 2 (02) becomes High.
The output of N4 becomes Low. The counter value (CNTi) becomes High when system clock 1 (01) becomes High. Accordingly, the output of N5 also becomes Low. But the input clock returns to be High, when the system is clock 1 (01) becomes High. Accordingly, the output of NR2 remains Low and the output of 5-Pi (i=o) also remains High. And the value of CNR1 remains High, since the output of N 5 is Low while the input clock is High. When the input clock (UPi-1 i=O) becomes Low, the output of 20 NR 2 becomes High, and the output of UF-i(i=O) becomes Low. If system clock 2 (02) is High, the output of CNR1 becomes Low, and the output of N4 becomes High. If the system clock 1 ((p,) is High, the output of CNTi becomes Low and the output of N5 becomes High. As mentioned above, the counter 3 starts to count up when the input of UTi-1 is Low, whereas the counter maintains its former state when the input of UFFi-1 is High. And the Wi outputs one Low in response to every two Low inputs of 5-Fi-1.
k 12 13 14 OUTPUT (Qn) 9102=199 11 02= 0 H L Qn-1 L H L Qn-1 L L H H L Qn-1 L L L H H Qn-1 H L (Table 1)
Fig. 6-2 shows the internal circuit of the CNR1 part of Fig. 6-1, and Table 1 shows the output status according to the input of 1,, 120 13 and 14.
Referring to Fig. 7-1, the operating mechanism of the comparative circuit can be explained. If the counter value (CNTi) is the same as the pulse width register value (PDRi), namely, both values are Low, the output of NR3 becomes High and NODE A becomes High. If both values of CNTi and PDRi are High, the NODE A also becomes High. However, if the values of CNTi and PDRi are different, namely, one is High and the other is Low, the output of NR3 becomes Low, accordingly, AND gate in ND, becomes Low and NODE A also becomes Low. If the counter value CNTi and the pulse width register value PDRi are the same and the value of E-Qi-1 is Low, NODE A is High and the output of N6 is High, therefore, the output of E-Qi becomes Low. In the other case that the values of PDRi and CNTi are different, or the value of E-Qi-1 is High, the output of E-Qi becomes High. This applies to each stage of the comparative circuit, so if the value of the counter and the value of pulse width register I(1) are the same on condition that the output of the pulse generator is Low, the output of EQ, 7 is Low, and the correspondence signal of EQI becomes High, and EQII becomes Low. If the output of the pulse generator is High on condition that the value of the counter and the value of the pulse width register 11(5) are the same, EQ117becomes Low and EQII becomes High. Namely, EQI = EQ,7OUTPUT NOR (EQ,7, OUTPUT) EQ= = EQ117OUTPUT NOR(EQI,7fbU---TPUT) Fig. 7-2 shows the internal circuit of ND1 in Fig. 7-1 and the Table 2 shows the output status according to the input of Ill I2f 13 and 14.
1 4 13 12 11 OUTPUT H H L H L H H L H L H L H L H L L L H (Table 2)
Referring to Fig. 5, the operating mechanism of the pulse generating circuit can be explained. As mentioned above, if the output of EQI is High and the output of EQ= is Low, the output of AND1 becomes High. However, since the output of AND2 is Low, flip-flop (F/F) is set.
Finally, the output of W1 becomes Low in synchronization with system clock 2(02), and the output of NR, becomes High. And the output of W2 becomes Low in synchronization with system clock 1 (01), and the output of N2 'S set to High. Since EQI is High, the CLR signal becomes High and the counter is cleared. Accordingly, both EQI and EQII become Low. Therefore, the flip-flop maintains its former state and the output of the pulse generator continuously remains High. If the value of the counter agrees with the value of pulse width register I(1) according to the counter's operation, EQ,7 becomes Low, but EQI still remains Low since the output of the pulse generator is High. When the counter value agrees with the value of pulse width register 11(5), E-Q-117 also becomes Low. The output of EQII becomes High since it is output by a NOR gate having inputs EQ117 and the inverse output signal of the pulse generator. And if EQII in the pulse generator becomes High, the flipf lop is reset according as the output of AND, is Low and the output of AND2 becomes High. The output of CN, becomes High in synchronization with system clock 2 (02) and the output of NR, becomes Low. The output of CN2 also becomes High in synchronization with system clock 1 (01) and the output of N2, namely, the pulse generator output is reset to be Low. The counter becomes cleared according as the output of OR, becomes High because EQII is High. According to the above mentioned operation, this programmable square wave generator outputs the wave as shown in Fig. 2. Herein, the equations for the period and duty cycle are as follows:
PERIOD = [ the value of pulse width register I(1) + the value of pulse width register II(S) + 2] x Tck DUTY CYCLE [the value of pulse width register 11(5) +11 x Tck Period X 100 (%) Fig. 8 shows the timing diagram of this programmable square wave generator. The Fig. 9 shows the operation flow chart of this embodiment. Referring to Fig. 9, the operation procedure can be explained. In the first step (100), the central processing unit (CPU) enables the 35- counter, and in the next step (101) the output of the pulse generator is tested whether it is High. If the - 8 output is not High, the following step (102) can be reached. in this step (102), the value of the counter and the value of the pulse width register, I(1) are compared. If these values are different, the value of the counter is increased in the following step (103) and the process returns to former step (102). If these values are the same, the output of the pulse generator is set (104) and the counter is cleared at the same time (108). If the output of the pulse generator is High in step (101), the value of the counter and the value of the pulse width register 11(5) are compared (105). If these values are different, the value of the counter is increased in the following step (106) and the process returns to former step (105). If these values are the same, the output of the pulse generator is reset (107) and the counter is cleared at the same time (108). Since these operations are continuously repeated, the output wave as shown in Fig. 2 can be generated.
k

Claims (2)

1. A programmable square wave generator for generating square waves, comprising:
two pulse width data registers for storing the pulse width values, counter, first comparator connected to a first one of said pulse width data registers and to said counter, for comparing the value of said first pulse width data register with the value of said counter, a second comparator connected to the second pulse width data register and to said counter, for comparing the value of said second pulse width data register with the value of said counter, and a pulse generator connected to said first and second comparators, whereby said pulse generator outputs a signal of a first level until the counter is equal to a value stored in said first pulse width data register and then outputs signal of a second level until the counter is equal to value stored in said second pulse width data register, thereby providing a square wave in which the period of the square wave and the duty cycle can be controlled by a program.
2. A programmable square wave generator substantially as hereinbefore described with reference to the accompanying drawings.
Publish d 1991 at 7be Patent Office. State House. 66/71 High Holborn, London WC I R47P. Further copies maybe obtained from ea Sales Branch, Unit 6. Nirn Mile Point. Cwmfelinfach. Cross Keys, Newport. NPI 7HZ. Printed by Multiplex techniques ltd. St Mary Cray. Kent.
GB9018147A 1989-08-17 1990-08-17 Programmable square wave generator Withdrawn GB2235103A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890011701A KR930000965B1 (en) 1989-08-17 1989-08-17 Programmable pulse generator

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GB9018147D0 GB9018147D0 (en) 1990-10-03
GB2235103A true GB2235103A (en) 1991-02-20

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JP (1) JPH03165620A (en)
KR (1) KR930000965B1 (en)
DE (2) DE4025378A1 (en)
FR (1) FR2651049A1 (en)
GB (1) GB2235103A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177373A (en) * 1990-09-28 1993-01-05 Kabushiki Kaisha Toshiba Pulse width modulation signal generating circuit providing N-bit resolution
EP0535615A2 (en) * 1991-09-30 1993-04-07 Nec Corporation Single chip microcomputer having two kinds of timer functions
US5631592A (en) * 1992-10-03 1997-05-20 Motorola, Inc. Pulse generation/sensing arrangement for use in a microprocessor system
US5793234A (en) * 1995-05-22 1998-08-11 Lg Semicon Co., Ltd. Pulse width modulation circuit
US7760120B2 (en) * 2007-06-27 2010-07-20 Thomson Licensing Generation method of a variable analogue signal generated by a PWM signal and system generating such a signal
CN101004430B (en) * 2006-01-16 2012-11-07 三星电子株式会社 Analog level meter and method of measuring analog signal level

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4121736C1 (en) * 1991-07-01 1993-01-07 Telefunken Electronic Gmbh, 7100 Heilbronn, De Switching pulses generating circuitry e.g. for vertical deflection in TV receiver - has oscillator with capacitor controlled from current sources and connected via terminal to integrated circuit
DE4123388A1 (en) * 1991-07-15 1993-01-21 Thomson Brandt Gmbh DEVICE FOR GENERATING VIBRATIONS AND THEIR APPLICATION
JPH1155084A (en) * 1997-07-29 1999-02-26 Matsushita Electric Works Ltd Output delay circuit
DE19842141A1 (en) * 1998-09-15 2000-03-16 Wilo Gmbh Function-generating control module for power transistors
DE10123742A1 (en) * 2001-05-16 2002-11-28 Siemens Ag Control and error correction for pulse output
KR100424311B1 (en) * 2001-12-17 2004-03-24 엘지전자 주식회사 Square-Wave Generator and Generating Method for the Same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076129A2 (en) * 1981-09-26 1983-04-06 Mitsubishi Denki Kabushiki Kaisha Circuit for generating pulse waveforms with variable duty cycles

Family Cites Families (3)

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Publication number Priority date Publication date Assignee Title
US3805167A (en) * 1972-06-27 1974-04-16 Telex Corp Digital pulse generator with automatic duty cycle control
JPS5445558A (en) * 1977-09-17 1979-04-10 Citizen Watch Co Ltd Frequency adjusting set for oscillator
JPS5533344A (en) * 1978-08-31 1980-03-08 Toshiba Corp Pulse generating device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076129A2 (en) * 1981-09-26 1983-04-06 Mitsubishi Denki Kabushiki Kaisha Circuit for generating pulse waveforms with variable duty cycles

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177373A (en) * 1990-09-28 1993-01-05 Kabushiki Kaisha Toshiba Pulse width modulation signal generating circuit providing N-bit resolution
EP0535615A2 (en) * 1991-09-30 1993-04-07 Nec Corporation Single chip microcomputer having two kinds of timer functions
EP0535615A3 (en) * 1991-09-30 1997-02-05 Nec Corp Single chip microcomputer having two kinds of timer functions
US5631592A (en) * 1992-10-03 1997-05-20 Motorola, Inc. Pulse generation/sensing arrangement for use in a microprocessor system
US5793234A (en) * 1995-05-22 1998-08-11 Lg Semicon Co., Ltd. Pulse width modulation circuit
CN101004430B (en) * 2006-01-16 2012-11-07 三星电子株式会社 Analog level meter and method of measuring analog signal level
US7760120B2 (en) * 2007-06-27 2010-07-20 Thomson Licensing Generation method of a variable analogue signal generated by a PWM signal and system generating such a signal

Also Published As

Publication number Publication date
JPH03165620A (en) 1991-07-17
KR910005566A (en) 1991-03-30
KR930000965B1 (en) 1993-02-11
FR2651049A1 (en) 1991-02-22
DE4026169A1 (en) 1991-04-04
DE4025378A1 (en) 1991-02-21
GB9018147D0 (en) 1990-10-03

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