DE4026169A1 - PROGRAMMABLE RECTANGULAR GENERATOR - Google Patents

Description

The invention relates to a programmable rectangular Wave generator, especially on a programmable one Rectangular wave generator, which is in a microcomputer Unit is arranged in which the period of the Square wave and pulse duration using a program can be controlled.

It is part of the state of the art, a time counter, which has a reload function in a circuit for To provide generation of the square wave, for one single chip, i.e. a micro-chip in the integrated Circuit technology. Such a known time counter works in such a way that an input value for the time counter is set by means of a microprocessor. Below this value runs towards zero, being a counting input signal of the time counter is counted. If this value becomes zero, so the periodic signal arrives at the output and leads to Implement a flip-flop. For such a counter can the period can be changed but the pulse duration is at 50% fixed.

Furthermore, a time counter is known, the pulse duration is changeable. The mode of operation is such that the output is set at the time when the value of a  Load register of the timer a counter reading of the timer reached. The output is reset at the time when the time counter overflows. With such a counter lies the pulse duration, however, only within a predetermined Period, or the pulse duration can be changed if the Time counter has an independent recharge function, however, only one pulse with a given one Pulse duration can be output.

The invention is therefore based on the object of being programmable Rectangle wave generator in a microcomputer unit provide in which both the period the square wave and the pulse duration using a Program can be controlled. Here the value a pulse width register is compared with the value of a counter. The programmable rectangular generator according to the invention contains two pulse width registers for determining the data the pulse width, a counter, two comparison circuits, a pulse generator and a data bus.

The invention will now be described with reference to the drawings explained. It shows

Fig. 1 is a block diagram of the invention,

Fig. 2 the output signal according to this invention,

Fig. 3 shows an example of the input signal of the counter,

Fig. 4 shows an example of the system clock,

Fig. 5 is a pulse generator and a control circuit according to this invention,

Fig. 6-1 the circuit of a counter according to this invention,

Fig. 6-2 increases the internal circuit of the CNR part of the counter circuit,

Fig. 7-1 a comparison circuit according to this invention,

Fig. 7-2 increases the internal circuit of the LP part of the comparison circuit,

Fig. 8 is a timing chart according to this invention,

Fig. 9 is a flow diagram of the operation of this invention.

As shown in Fig. 1, the programmable square wave generator according to this invention includes a pulse width register I ( 1 ), a comparator circuit I ( 2 ), a counter ( 3 ), a second comparator circuit II ( 4 ), a second one Pulse width register II ( 5 ), a pulse generator ( 6 ) and a data bus ( 7 ). The structures and functions of this programmable rectangular wave generator are explained below on the assumption that it is designed as a peripheral device of a microcomputer unit. The central processing unit (CPU) supplies the data to determine the width of the low level of the square wave in the pulse width register I ( 1 ) and also the data to determine the width of the high level of the square wave signal in the pulse width register II ( 5 ).

When the CPU enables the counter ( 3 ), the counter starts counting down based on the received input clock signals (CK). As can be seen in connection with Fig. 6-1, the operation of the counter ( 3 ) can be explained on the assumption that the input clock has the same pulse shape as shown in Fig. 3. The input clock pending at the beginning is led to -1 (i = 0). The initial switching states of the individual parts of the counter are set as follows, with "High" being written for high level and "Low" for low level: CLR is set to high, the output from CNR is low, the output from N 4 is high, the output of CN 4 is low, the output N 5 is high, the output of NR 2 is low and the output of N 3 is high. From the initial state, CLR goes low and the counter starts to work. In the event that the input clock is high, the output of NR 2 remains low. As long as the input of CNR 1 , namely at the AND part with the input clock and the output from N 5 is high, the output from CNR 1 remains low, and as long as the system clock 2 (Φ₂) is high. When the input clock goes low, the output from NR 2 remains low without changing.

On the other hand, the output of CNR 1 becomes high when the AND gate of CNR 1 goes low and the system clock 2 (Φ₂) becomes high.

The output of N 4 becomes low. The value (CNTi) of the counter goes high when the system clock 1 (Φ₁) becomes high. Accordingly, the output of N 5 also goes low. On the other hand, the input clock returns to high, correspondingly when the system clock 1 (Φ₁) becomes high. In addition, the output of NR 2 remains low and the output of (i = 0) also remains high. Furthermore, the value of CNR 1 remains high while the output from N 5 becomes low, corresponding to how the input clock remains high. According to how the input clock = 0) becomes low, the output of NR 2 becomes high and finally the output of OFi (i = 0) becomes low.

In the event that system clock 2 (Φ₂) is high, the output from CNRI becomes low and the output from N 5 becomes high. In the event that the system clock 1 (Φ₁) is high, the output CNTi becomes low and the output from N 5 to high. As already mentioned above, counter 3 starts counting when the input is from -1 to low, while the counter remains in the assumed state when the input is from -1 to high. Furthermore, the output signal becomes a low in response to two low input signals at -1.

Table 1

Fig. 6-2 shows the internal circuit of CNR 1 of Fig. 6-1, and in Table 1, the output state corresponding to the inputs I₁, I₂, I₃ and I₄ is shown. L is the switching state Low and H the switching state High.

The operation of the comparator circuit will be explained with reference to FIG. 7-1. If the counter value (CNTi) is the same as the value (PDRi) of the pulse width register, and if both values are low, the output of NR 3 becomes high, and the signal high is present at network node A. If both values of CNTi and PDRi are high, then the high signal is also present at network node A. If, however, the values of CTNi and PDRi are different, one being high and the other low, the signal Low is also present at the output of NR 3 . Accordingly, the AND gate in ND 1 becomes low and the signal at node A also becomes low. In the event that the value CNTi of the counter and the value PDRi of the pulse width register are the same, provided that the value is from -1 to low, the signal at node A is high, with the output of N 6 likewise is high so that the output goes from to low. In the other case, the values of PDRi and CNTi are different, provided that the value of -1 is high, the output of becomes too high. Here EQi-1 (i = 0, -1) applies, and the first area of the comparator circuit keeps the signal low. Now if the value of the counter and the value of the first pulse width data register I ( 1 ) are the same, provided that the output of the pulse generator is low, the output from EQI₇ to low. Eventually the corresponding signal from EQI becomes high and EQII becomes low. In the event that the output of the pulse generator is high, provided that the value of the counter and the value of the second pulse width data register II ( 5 ) are equal, it will go low, while EQII will go high . The following therefore applies:

In Fig. 7-2, the internal circuit of ND 1 of Fig. 7-1 is shown customer in the following Table 2, the switching state corresponding to the inputs of I₁, I₂, I₃ and I₄ is shown.

Table 2

The mode of operation of the pulse generation circuit is explained with reference to FIG. 5. As already mentioned above, the signal High is present at the output of the AND if the output from EQI is high and the output from EQII is low. Thus, since the output from AND is low, the flip-flop (F / F) is set. Furthermore, the output of CN 1 becomes low in synchronization with the system clock 2 (Φ₂) and the output of NR 1 receives the signal value high. The output of CN 2 becomes low in synchronization with the system clock 1 (Φ₁) and the output of N 2 is set to high. Since EQI takes the signal value high, the CLR signal becomes high and the counter is enabled. As a result, the two signals EQI and EQII become low. Therefore, the flip-flop maintains the previous switching state and the output of the pulse generator remains high at the signal value.

If the value of the counter coincides with the value of the pulse width data register I ( 1 ), in accordance with the effectiveness of the counter, where will go to low, but EQI still maintains the signal value low because the output of the pulse generator is high. In the event that the value of the counter matches the value of the pulse width data register II ( 5 ), EQII₇ also becomes low. The output of EQII becomes high because it forms the output of the NOR gate at the input of EQII₇ and the inverted signal of the pulse generator. When EQII in the pulse generator reaches the signal value high, the flip-flop is reset, accordingly the output from AND 1 becomes low and the output from AND 2 becomes high.

The output of CN 1 becomes high in synchronization with the system clock 2 (Φ₂) and the output of NR 1 becomes low. The output of CN is also high in synchronization with the system clock 1 (Φ₁) and the output of N 2 , namely the pulse generator, is reset to low. The counter is enabled as soon as the output of OR 1 reaches the signal value high, since EQII takes the signal value high. In accordance with the mode of operation explained above, the programmable square wave generator generates an output signal, the form of which is shown in FIG. 2. According to the invention, the following conditions apply to the period and the pulse duration:

Period duration = [value of PBR I ( 1 ) + value of PBR II ( 5 ) + 2] × Tck

with PBR I the first pulse width data register and with PBR II denotes the second pulse width data register II becomes.

Figure 8 shows the timing diagram of this programmable square wave generator. Fig. 9 shows the flow chart of this invention. The mode of operation will be explained with reference to FIG. 9. In a first step ( 100 ) the central processing unit (CPU) activates the counter and in a next step ( 101 ) the output of the pulse generator is queried whether it assumes the signal value High. If the output is not high, the next step ( 102 ) can be carried out. In this step ( 102 ) the values of the counter and the value of the pulse width register I ( 1 ) are compared with one another. If these values are different, the value of the counter is incremented in the subsequent step ( 103 ) and it is returned to the previous step ( 102 ). If these values are then the same, the output of the pulse generator is set in step ( 104 ) and the counter is released at the same time ( 108 ). If the output of the signal generator takes the value High in this step ( 101 ), the value of the counter and the value of the pulse width register II ( 5 ) are compared ( 105 ). If these values are different, the value of the counter is increased in a subsequent step ( 106 ) and the process is returned to the previous step ( 105 ). If the values are the same, the output of the pulse generator is reset ( 107 ) and the counter is released at the same time ( 108 ). Since these functions are repeated continuously, the output signal curve according to FIG. 2 can be generated.

Claims (6)

1. A programmable square wave generator for generating square waves,

• with two pulse width data registers for storing the values of the pulse widths,
• - with a counter,
• with a first comparator which is connected to one of said pulse width data registers and to said counter in order to compare the value of one of said pulse width data registers with the value of said counter, and
• with a second comparator, which is connected to the second of said pulse width data registers and to said counter,
• with a pulse generator connected to the first and second comparators,

said pulse generator

• outputs a high signal until the counter reaches a value which is equal to a value stored in the first-mentioned pulse width data register,
• and then outputs a low signal until the counter reaches a value which is equal to a value stored in the second pulse width data register,
• - whereby a selectable pulse duration is achieved, which is controlled by a program in which the period of the square wave and the pulse duration can be controlled by the program.

2. A programmable square wave generator, in which the period of the square wave and the pulse duration are controlled by means of a program which compares the value of a pulse width register with the value of a counter, is characterized by:
a pair of pulse width registers ( 1, 5 ) for recording the data of the pulse width,
a counter ( 3 ) to count the received clock pulses,
a pair of comparator circuits ( 2, 4 ) to compare the value of the pulse width register ( 1, 5 ) with the value of the counter ( 3 ),
a pulse generator ( 6 )
and a data bus ( 7 ). 3. Programmable square wave generator according to claim 1 or 2, characterized in that the counter ( 3 ) and the two pulse width registers ( 1, 5 ) are connected to the data bus ( 7 ), in particular the counter ( 3 ) clock signals (CK) can be supplied that the comparator circuit ( 2, 4 ) is provided between the counter ( 3 ) and each of the two pulse width registers ( 1, 5 ), the signals (EQ I and EQ II) of the pulse generator ( 6 ) can be supplied . 4. Programmable rectangle generator according to claim 1 or 3, characterized in that the period is determined according to the following equation: Period = = value of PBR I ( 1 ) + value of PBR II ( 5 ) + 2] × Tckw those with PBR I the first pulse width register and PBR II is the second pulse width register. 5. Programmable square wave generator according to one of claims 1 to 4, characterized in that the pulse duration is determined according to the following equation: PBR II being the second pulse width register.