SU1492470A1 - Majority multiplexer - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital computers and specialized computing devices. The purpose of the invention is to provide automatic selection of the mode of operation. To achieve the goal, the device includes triggers 2.1, 2.2, elements OR-NOT 3.4, elements OR 5.6, elements AND 7.8, elements NOT 9.10, counters 11,12,13, and elements 14,15 delays. The device also contains input buses 16,17,18, major multiplexer unit 1 and output buses 19. This device provides automatic transition from the three-channel operation mode to the single-channel operation mode, from the single-channel operation mode to another channel or return to the operation mode with three channels depending on changes in the external environment. 1 dw., 2 tab.

Description

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The invention relates to the pulse technique and can be used in digital computers and associated computing devices,

The purpose of the invention is to provide automatic selection of the operating mode, which is achieved by introducing new design features that provide automatic transition to work from one channel to another or work simultaneously with three channels depending on changes in the external environment.

The drawing shows the scheme of the major-multiplexer device.

The majoritarian-multiplexer device contains a major-multiplexer unit 1, the first 2.1 and second 2.2 triggers, the first 3 and second 4 elements OR NOT, the first 5 and second 6 elements liflU, the first 7 and second 8 elements And, the first 9 and the second 10 items are NOT, the first is the third counters 11-13, the first 14 and the second 15 are delay elements, the first is the third input bus 16-18 and three output bus 19.

The three output buses 19 are connected respectively to the three outputs of the majoritarian-multiplexer unit 1. The input buses 16 to 18 are connected respectively to the clock inputs of the counters 11 to 13. The overflow output of the counter 11 is connected to the first inputs of the AND 7 element, the OR-HE element 3 and the element OR 5, the output of which is connected to the inputs of the delay elements 14 and 15, the outputs of which are connected respectively to the clock inputs of the flip-flops 2.1 and 2.2 and the reset inputs of the counters 11 to 13. The output of the full 1W counter 12 is connected to the input of the HE element 9, to the second input and OR 5 and with the first input of the element OR- NO 4, the output of which is connected to the second input of the element OR-NOT 3. The overflow output of the counter 13 is connected to the third input of the element OR 5, to the second input of the element ШИИ-НЕ 4, to the first input of the element And 8 and the input element is NOT 10, the output of which is connected to the second input of the element And 7, the output of which is connected to the first input of the element OR 6, the second input of which is connected to the output of the element And 8, the second input of which is connected to the output of the element NOT 9.

The outputs of the elements OR 6 and OR-NOT 3 are connected respectively with information

trigger inputs 2.1 and 2.2, the outputs of which are connected respectively to the tenth and eleventh inputs of the majority-multiplexer unit 1, the first, fourth and seventh inputs of which are connected to the input bus 16. The input bus 17 is connected to the second, fifth and eighth inputs

Q majority-multiplexer unit 1, the third, sixth and ninth inputs of which are connected to the input bus 18.

Majority-multiplexer unit

5 1 functions as three ma; horitar, if the zero code enters its tenth and eleventh inputs. The receipt of a different code translates the major-multiplexer unit 1 into one-channel mode of operation. The dependence of the output signals of block 1 on the input signals is given in table. one.

Designations adopted in Table. 1: D1 - the first input of the majority-multi5 plexor unit, D2 - the third input, DZ - the second input, D4 - the fourth input, D5 - the sixth input, D6 - the fifth input, D7 - the seventh input, D8 - the ninth input, D9 - the eighth entrance, A1 - the first decade, L2 - the eleventh entrance,

U1 is the first exit, U2 is the second exit, UZ is the third exit.

The device works as follows.

In the initial state, the triggers 2.1, 2.2 and the counters 11-13 are in the zero state (the setup bus is not shown). Upon receipt of 16–18 input pulse sequences on buses, the corresponding counters 11–13 calculate them.

When one or two of the counters 11-13 overflow in triggers 2.1 and 2.2, representing a two-bit register, the code is set different from zero, and the Majority-Multiplexer unit 1 goes into single-channel mode of operation. On the output buses 19 of the device, the information of that channel appears,

 corresponding to the counter whose counter was overflowed. The overflow signal of any of the counters 11-13 through the first element OR 5 enters the delay elements 14 and 15. From the output of the delay element 14, the signal arrives at the clock inputs of the trigger 2.1 and 2.2, and the information arriving at the information inputs of the trigger 2.1 is captured.

five

0

five

5U

and 2.2. But the signal from the output of the element 15 delay resets the counters 11-13.

In the case of a single overflow of counters 11-13, the triggers 2.1 and 2.2 are set to Hy; i.e., the BoE state, and the majority-multiplexer-KYR1 unit 1 operates in the normal majoritarian mode.

The change in the state of triggers 2.1 and 2.2, depending on the overflow signals of the counters 11-13, is determined by the following zero functions

A XZ-i-ZY

(Y + Z),

where X is the overflow signal from counter 11; Y is the overflow signal from counter 12;

Z is the overflow signal from counter 13;

A - signal at trigger output 2. 1 V - signal at trigger output 2.2

The signals X, Y, Z are equal to zero if there was no overflow on the corresponding counter, and they are equal to one if the overflow is a beating.

The correspondence between the overflow signals at the output of the counters 11-13 and the signals from the outputs of the flip-flops 2.1 and 2.2 is given in table. 2

The counter size 11–13 is determined by the specific application of the device in three-channel logical structures. The counter size is determined by the maximum operating time of the system into which the device enters without significant disturbance when working with a faulty channel (only a break type is considered here).

Thus, in the proposed device, an automatic transition from one channel to another or operation simultaneously with three channels depending on changes in the external environment is provided. The device provides an automatic transition (returned) to work with a previously rejected channel and subsequently restored.

Claims (1)

Invention Formula A majoritarian-multiplexer device containing three input buses, three output buses, and a majority-multiplexer , " 15 20 25 20 35 0 0 five 706 typlex 6; ioK, first, BTOpoii, third, Thursday 1 1, six, seventh 1 1, eighth, ninth, tenth and eleventh inputs, three outputs of the majority-multiplexer unit are connected by corresponding} 1o with three output buses, characterized in that, in order to ensure the automatic selection of the mode of operation, two triggers, two NOT elements, two AND elements, two OR elements, two OR-NOT elements, two delay elements, first, second and third counters, clock the inputs of which are connected respectively with the first, second and third in one bus, the overflow output of the first counter is connected to the first inputs of the first element AND, the first element IlTOi-HE and the first element OR, the output of which is connected to the inputs of the first and second delay elements, the outputs of which are connected respectively to the clock inputs of the trigger and the reset inputs of the counters, output the overflow of the second of which is connected to the input of the first. element NO, with the second input of the first element IL llI and with the first input of the second element iUlll-HE, the chimney of which is connected to the second input of the first element lUDl-fii ;, the overflow output of the track counter is connected to the third input of the first element OR, with the second input The second element MLI-NOT, with the first input of the second element AND and the input of the second element NOT, the output of which is connected to the second input of the first element I. And the output of which is connected to the first input of the second element OR, the second input of which is connected to the output of the second element AND, entrance to second is connected to the output of the first element NOT, the outputs of the second element OR and the first element of the IPD-NOT are connected respectively to the information inputs of the first and second triggers, the outputs of which are connected respectively to the tenth and eleventh inputs of the majority-multiplexer unit, the first, fourth and seventh inputs of which connected to the first input bus, the second input bus connected to the second, fifth and eighth inputs of the majority-multiplexer unit, the third, sixth and ninth inputs of which are connected to the third input oh by bus. Table 1 Table 2