SU1492365A1 - Teaching device - Google Patents

Abstract

The invention relates to automation and computing and can be used in the organization of training in educational institutions. The purpose of the invention is to expand the didactic capabilities of the device. The goal is achieved by the fact that the device containing the consoles 3 students, switches 1 and 2, registers 19, 20, generator 6, delay elements 8, 9, unit 21 for presenting educational information, unit 12 comparisons, counters 5, 7, triggers 4, 18, elements And 14, 16, 17, decoder 13, element OR 15. 1 Il.

Description

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Of (), the issue is related to automation and computer technology and can be used to organize training in distinguishable educational institutions.

The purpose of the invention is to expand the didactic capabilities of the device. The drawing shows a structural diagram of the proposed device.

The device contains switches 1 and 2, the learners' consoles 3, trigger 4. counter 5, generator 6, counter 7, delay elements 8 and 9, element 10, block AND memory, block 12 compare, decoder 13, elements 14, the element OR 15, the element AND 16, the ment And 17, the trigger 18, the registers 19 and 20, the block 21 of the presentation of educational information, the amplifiers 22, the indicators 23.

The device works as follows.

In the initial state, the device memory elements were reset. A trigger 4 with a signal from its zero output keeps the counter 5 in the zero state and prepares element 10 for opening. After turning on the generator 6, pulses successively fill the counter 7, which through switches 1 and 2 polls the corresponding outputs of the consoles 3, and through the decoder 13 - elements AND 14, In addition, the pulses of the generator 6, held by element 9, through the elements AND 10, OR 15 are fed to elements AND 14, sequentially opening them. From the output of the AND 14 elements, the clock pulses are applied to the clock inputs of the corresponding bits of the registers 19 and 20. Since the flip-flop 18 is in the zero state and the AND element 17 is closed, the bits of the registers 19 and 20 are also set to the zero state.

Each student on his console 3, after solving his own variant of the task, sets the response code supplied to switch I, and also sends an input signal to the input of switch 2. The switch 2 signal sets the trigger to one state, stopping counter 7, closing element 10, preparing elements 16,17 for opening and allowing counter 5 to work. The state of counter 7 corresponds to pulse 3, from which the answer is currently being entered, and pre

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The counter 5, counting the clock cycles of the generator 6, issues successively in the block 11 of the address. The control input of block 1I receives a read pulse delayed by the time of setting the address. In the memory cells of the block I, the decision codes of one variant of the job are stored.

In the case of the etching task at the output of block 12, a signal is formed that sets the trigger 18 to the unit state, supplying the unit to all bits of the register 20. After the counter 5 overflows with the signal through the elements AND 16, OR 15, the unit 20 is written to the corresponding decoder 13 including indicator 23 It is true that it corresponds to the required console 3. After the time determined by element 8, triggers 4 and 18 nullify. Trigger 4 resets counter 5 and enables counter 7 to interrogate remotes 3.

If the task is incorrectly solved, the trigger 18 remains in the zero state, the register level 19 through the element 17 exposes a unit-level signal displayed in block 21 on the corresponding console 3 indicator 23, signaling an incorrect response to this task.

Claims (1)

Invention Formula A teaching device that holds the learning consoles, the information outputs of which are connected to the corresponding SOUTH inputs of the first switch, the outputs of which are connected to the corresponding inputs of the first I pyniibi comparison unit, the inputs of the second group of which are connected to the corresponding outputs of the memory block, the group of terminals AND, the outputs of which are connected to the corresponding control inputs of the lepHo and second registers, the second switch, the generator, the delay elements and the unit of presentation of educational information, characterized in that expanding the didactic capabilities of the device, the first and second counters, the first and second triggers, the first, second and third elements AND, the decoder and the OR element, the first and second inputs of which o are connected to the outputs of the first II second elements AND, and the output with the first inputs of elements AND of a group, the second inputs of which are connected to the corresponding outputs of the decoder, the inputs of which are connected to the corresponding outputs of the second counter connected to the corresponding control inputs of the first and second to switching inputs, the information inputs of the second switch are connected to the sync outputs of the respective learning consoles, and the output is connected to the S input of the first trigger, the zero output of which is connected to the initial input of the counter and the first A The first input of the first element is AND, the unit output is to the first inputs of the second and third elements AND to the control input of the second counter, and the R input is connected to the output of the first delay element connected to the R input of the second tri1-ger, whose S input is connected With the output of the comparator unit, the single mouse mode is with the control input of the second register, and the zero H1.1 input - with the second input of the third element I, the output of which is connected to the control input of the first register, the outputs of the first and second registers are connected respectively to the inputs the first and the second group of the instructional information presentation unit, the POWN of the second element I is connected to the input of the first delay element, and the second input is connected to the overflow output and the control input of the first counter, whose information outputs are connected to the corresponding address inputs of the memory block, and the information input with the output of the generator, the information input of the second counter and the input of the second delay element, whose input is connected to the control input of the memory unit and the second input of the first element I,