SU1399801A1 - Operator training apparatus - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to train the operational memory of the operators of automated control systems. The simulator contains the first 1 and second 4 blocks of instructional training information, a divider 2 frequencies, an operator console 3, a response analysis block 5, a pseudo-random pulse trainer 6, a control block 7, an indication block 12, a timer 11 and three registers 8.9,10. The device provides operator training that helps detect the amount of RAM when the number of monitored variables changes by abruptly changing the number of confusing stimuli (monitored variables) while gradually changing the number of informational stimuli (RAM size) as positive results are achieved. 5 hp f-ly, 6 ill. (L

Description

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The invention relates to automation and computing and can be used to train the RAM of automated control systems operators.

The circuit of the invention is the expansion of the didactic capabilities of the device by providing operator training that helps detect the amount of RAM when the number of monitored variables changes, by abruptly changing the number of interfering stimuli (monitored variables) while gradually changing the number of information stimuli (RAM) achieve positive results

Figure 1 shows the functional diagram of the device; FIG. 2 is a functional electrical circuit of the instructional information setting block of FIG. 3 is a frequency divider circuit; Fig, 4 is the same, the block of analyzes of the answers in Fig "5 is the same, the timer; on fig.b - the same, control unit

The device contains a block 1 setting educational information, a frequency divider 2, an operator’s console 3, a block 4 setting educational information, a response analysis block 5, a pseudo-random pulse trainer 6, a control block 7, registers 8,9,10, a timer 11, a display 12 ,

Blocks 1 and 4 include a counter 13, shifting the register 14, the element I 15, the element ШШ 16, the trigger 17, the element 18 ban.

The structure of the divider 2 includes t counters 19,20,21, trigger 22, the element 23 of the ban.

The block 5 includes elements AND 24, elements OR 25.26, counter 27, elements AND 28, and one-shot 29.

The timer 11 includes a generator of 30 clock pulses, elements AND 31, accumulative elements 32, trigger 33.

The block 7 includes a pulse shaper 34, a shift register 35, triggers 36 and 37, elements 38.39, delay element 40, generator 41.

The device works as follows.

When the power is turned on, all elements of the device are reset. When you press the Start button on the remote 3 pulse from its output

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arrives at the input of the trigger 33, sets it to the unit state, which ensures the start of the generator 30, to the input of the register 10, writes 1 to its first bit, and to the inputs of blocks 1 and 4, writing 1 to the central bit of the registers 14. Single the potential from the first output of register 14 of block 4 is fed to the input of element 28, preparing a circuit for passing a correct response pulse to one interfering stimulus. The unit potential from the output of register 10 is fed to the input of timer 11, setting the minimum speed for presenting the clock pulses generated by the generator 30, and to the input of unit 12, highlighting the indicator of the numerical value of the speed for presenting stimuli.

After passing the first pulse from the imager 6, through the information input of the element 18, to the prohibiting input of which from the output of the trigger 17, a zero potential is applied, to the register 8, which follows the 1cm fifth impulse from the output of the merchant 6 to the input of the counter 13 and causes the appearance of a single potential at its output, which through the element 15 and the element OR 16 enters the single input of the trigger 17. The unit potential from the output of the trigger 17, applied to the prohibition of the input of the element 18, stops the flow of the pulses from the output of the sensor l 6 in register 8.

After the passage of the first pulse from the output of the imager 6, through the information input of the element 18 of block 4, to the prohibiting input of which from the output of the trigger 17, a zero potential is applied, to the register 9, the first pulse following it from the fourth output of the imager 6 enters the input of the counter 13 and causes the appearance of a single potential at its first output, which through elements 15 and 16 enters the input of the trigger 17. The unit potential from the output of the trigger 17, applied to the prohibitive input of element 18, stops the flow of pulses from the third The output of the former 6 to the register 9. The unit potential from the output of the register 9 is fed to the inputs of the unit 5. Thus, the task of a certain number of information and interfering stimuli is provided.

When the generator 30 is turned on in timer 11, the first three clock pulses provide automatic control of the simulator's working capacity, and every four subsequent ones - a work cycle

When the first clock pulse arrives from the output of timer 11 to the input of block 7, a pulse appears at the output of the last one, which turns on the Response indicator at block 12, and entering the input of remote control 3, allows the operator to enter a response. The next pulse following it from the output of block 7 is fed to the input of block 2 and to the input of register 9, setting it back to its original state and preparing to fill the new pulse sequence, to the input of block 5, setting counter 27 to its initial position, ie, to the inputs of blocks 1 and A, setting the counters 13 to the initial state, and the triggers 17 to the zero position. On the indicator of block 12, O cycles is displayed.

When the second clock pulse arrives, the pulse sent from the output of block 7 to the input of block 8 ensures the arrival of unit potentials from its outputs to the inputs of block 12, and a pulse, subunit from the output of block 7 to input of block 9, ensures the flow of unit potentials from its outputs to the inputs of block 12, highlighting the last information on the indicators

Potential from the output of block 7 is fed to the input of register 8, ensuring the passage of signals from the outputs of the register

The 8th inputs of the block 12 and the display on the indicator of a combination of five informational 171 presented to the learner for storage. At the end of the first clock pulse of the first cycle, the presentation of information-1D

The second clock pulse of the first circuit does not cause changes in the circuit, since only at the first output of block 7 there is a single potential.

The third clock pulse of the first cycle occurs at the outputs of the unit 7 unit potentials, which are applied to the corresponding inputs of registers 8 and 9 and carry the signals (unit potentials) from the outputs of registers 8 and

9 on the inputs of block 12, highlighting informational and disturbing indicators on indicators, against the background of information, searches for an interfering stimulus and remembers. At the end of the third clock pulse of the first cycle, the display of stimuli stops on

The fourth clock pulse of the first cycle is observed at the output of unit 7 of a single potential, which provides exposure to the unit.

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and interfering stimuli. 11 impulse, filed 12 Response indicators and allowing from block 7 output to block 2 input, us- console 3 operation, trained by

22 to zero by the buttons of the remote control 3 reproduces the disturbing stimulus.

If the student correctly reproduces the interfering stimulus and is laid down in time, then the pulse of the output of the console 3 is fed to one input of the element 24, to the other input of which the unit potential is fed from the output of the register d 9, the pulse from the output of the element 24 goes through the element 25 to the input of the counter 27, ensuring the appearance of a single potential at its output, which is applied to the input of the first element 28, through element 26 enters the input of a single vibrator 29 (with a potential input), causing the appearance at the output of the last pulse. This impulse is fed to the input of block 2, fixing the first correct answer in the counter 19, and flips the trigger 22 to a single position, ensuring the supply of a single potential to the prohibiting input of the element 23,

dips trigger L2. to zero position.

When the third clock pulse arrives, processes similar to the arrival of the first clock pulse occur in the device, but the pulse from the output of block 7, which enters the input of block 2, passes through element 23 to the input of counter 19 and sets the latter to the initial state. This completes the monitoring of the health of the simulator.

The first clock pulse of the first cycle from the output of the generator 30 provides the appearance on the first and second outputs of unit 7 of single potentials. The unit potential through transformer 34 is converted into Los into a short pulse and from unit 7 is fed to the input of unit 12, fixing the first cycle in the indicator, and at the input of the imager 6, changing the sequence at its outputs. Unit

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prevents meter counter 19 when the unit potential from the output of block 7 “

After the end of the fourth clock pulse of the first button, at the output of block 7, a single potential appears at the inputs of registers 8 and 9, returning them to the initial state, to the inputs of blocks 1 and 4, returning counters 13 to the initial state and transferring the triggers 17 to the zero position, thereby preparing registers 8 and 9 to fill the new pseudo-random sequence and mycoB, to the input of block 5, returning to the initial state counter 27, and to the input of block 2 - information input of element 23, Pa this ends the first loop,

Upon receipt of the first clock pulse of the second lanuia, the unit potential from the output of block 7, transforming the forge n-34 actuator into short and flylyc, enters the input of the imager 6, changing the pulse sequence at its outputs and to the input of block 12, fixing the following in the indicator . The same number of stimuli will be presented to the trainee, but in a different sequence.

The operation of blocks and elements in after cycles is similar to that described above.

If the learners did not correctly reproduce the interfering or did not fit in time, then the zero potential at the output of block 5 will not change, from the output of the trigger 22 to the inhibitory input element 23 the zero potential is applied. After the end of the second cycle, the impulse from the output of the block 7 through the element 23 is fed to the input of the counter

19, setting the latter to its original state.

If the trainee answered five times correctly, then the fifth correct pulse from the output of block 5, received at the input of counter 19, causes the appearance at the output of the last overflow pulse. This impulse arrives at the input of register 14 by moving the unit from the first exit to the second exit and ensuring that the forzhfatel 6 exits the six registers and six informational stimuli from the output 8 and the counter

20, by registering in the last unit of the same pulses the counter 19 is set to the initial state.

The operator (learner) will be presented with six informational and one disturbing stimulus. Each fifth correct answer will write one Jty unit into counter 20 and increase the number of informational stimuli by one to ten with one interfering stimulus.

If the operator responds correctly with ten informational and one interfering stimuli five times a second, then the overflow pulse from the output of counter 19, received at the input of the register 14 of unit 1, will move the unit from the sixth output (the tenth digit) to the first output ( Fifth bit), having supplied the output of shaper 6 to the input of the register 8, five informational stimuli, and the impulse received to the input of the counter 20 causes the appearance of an overflow pulse at its output, KOTopbui enters the input of the register 14 of the block. 4 and moves the device from the first output to the second input, supplying the output of the imaging unit 6 to the input of the register 9 of two Meuiaiouptx stimuli,. At the same time, the pulse from the counter code 20 enters the counter 21 and fixes a unit in it, I.-Tulsaml from its outputs are counters 19 and 20 are reset.

A unit income from the code of register 1 and 14 of unit 4 is fed to the input of the second element 28, preparing the circuit for passing the impulse of the correct response to two interfering stimuli.

The trainee will be presented with five informative and two disturbing symbols. With the correct identification and reproduction of both interfering stimuli at the output of the one-shot 29, the impulse of the correct response appears. Each fifth correct answer writes the unit to counter 20 and increases the number of informational stimuli by one to ten with two interfering stimuli, and then with three interfering stimuli.

On the fifth correct answer, with ten informational and three interfering stimuli, the pulse from the output of counter 19 moves the unit in register 14 of block 1 from the sixth output to the first output, the pulse from the output of counter 20 moves the unit in register 14 of block 4 from the third output to first exit , and the pulse that appears at the output of counter 21 goes to

input register 10 and moves one-from the first output to the second output. The unit potential from the second output of the register 10 highlights on the indicator of block 12 a digit of a higher rate of presentation of stimuli, and by entering the input of timer 11, it increases the rate of presentation of clock pulses from the output of generator 30.

The operator with the above described sequence will be presented with informative and interfering stimuli. After the second speed increase (if the student correctly searches for interfering stimuli), a pulse appears at the output of register 10, which arrives at trigger input 23, expelling zero potential from the last generator 30, and at input 12, highlighting the indicator Co - nets.

The use of the invention in devices for training the memory of operators of automated control systems makes it possible to more fully reveal the amount of RAM, i.e. the operator’s ability to absorb and retain the input information and, the volume of which is changed by increasing the number of stimuli from the minimum to maximum averaged value by gradually increasing the number of information stimuli presented in a random sequence in which one, two or three interfering stimulus. The process is repeated until five times the correct presentation of the presented information.

According to the number of informational and interfering stimuli that the trainee correctly recognizes over a certain time, taking into account the speed of presentation (response), determine the amount of RAM, the operator and his ability to process data logically in a random spatial distribution of stimuli.

This technical solution is most appropriate to use when training and studying the memory of operators of complex ACS, in which there are controlled variables of a random nature.

Claims (1)

Claim 1 1. Device for training operators, containing a remote operator. /, 0 five " 0 five 0 whose input is connected to the first output of the control unit, the second output of which is connected to the input 1 of the 1st pseudorandom pulse trainer and the first input of the display unit, the second input of which is connected to the first output of the control unit, the input of which is connected to the timer output, and the response analysis unit, characterized in that, in order to expand the didactic capabilities of the device, the first and second blocks of the instructional information, the frequency divider, the first) second and third registers are entered into it, and The third, third and fourth pykhody of the third register are connected respectively to the third, fourth, fifth and sixth inputs of the display unit and the first, second, third and fourth inputs of the timer, the fifth input of which is connected to the control output of the operator console connected to the first information inputs of the first and second blocks of the instructional educational information and the information input of the third register, the clock input of which is connected to the first output of the frequency divider, the second and third outputs of which are connected to the clock inputs of the corresponding First and second blocks of instructional information, and information and first and second control inputs, respectively, to the output of the response analysis block and the third and fourth outputs of the control block, the fifth output of which is connected to the clock input of the first register, whose information input is connected to the output the first block of the instructional information, and the outputs to the corresponding inputs of the first group of the display unit, the inputs of the second group of which are connected to the corresponding outputs of the first group of the second register, t The output of the control unit is connected to the clock input of the second register, and the fourth output to the installation inputs of the first and second blocks of the instructional information, the first and second registers and the response analysis block, the information inputs of the first, second and third groups of which are connected respectively to the information outputs of the console the operator, the outputs of the group of the second block of the instructional information and the outputs of the second group of the second register, the informatdion input of the second register is connected to the output of the second block of the instruction of information, the second and third information inputs of which are connected respectively to the first and second outputs of the I1 pulses pseudo-random sequence generator, the third and fourth outputs of which are connected to the Third and third information inputs of the first block, respectively, setting educational information about 2o The device according to 1, which means that the block sets the NIN instructional information containing a counter, the C and R inputs of which are quantified with the first information and the setting inputs of the block, respectively, and the outputs are connected to the first inputs The corresponding elements AND, the second inputs of which are connected to the corresponding outputs of the shift register, the clock and information inputs of which are respectively the clock and second information inputs of the block, respectively, the OR element, whose inputs are connected to the outputs of the corresponding Their elements are And, and the output is to the S input of the trigger, the R input of which is connected to the corresponding input of the counter, and the code of the trigger input of the BAN element, the information input and output of which are the third information input and output of the block, respectively. shift register are the corresponding outputs of the block group. 3. The device according to claim 1, that the frequency divider contains the first counter, the C input of which and the S input of the trigger are the input of the divider, the R input is connected to the output of the element BAN, and the output is the second output of the divider and connected to the input of the second counter, the output of which is the first output of the divider and connected to the input of the third, counter, the output of which is the third output of the divider, the control input of the BANNER element the input of the divider, and the information input is connected to the trigger output, R- the input of which is the second control input of the divider. A device according to claim 1, characterized in that the analysis unit Q 5 Q 5 Q - five 0 five after the mark it contains the elements of the first group I, the first and second inputs of which are the corresponding information inputs of the first and third groups of the block, and the outputs are connected to the corresponding inputs of the first OR element, the output of which is connected to the C input of the counter, the R input of which is the installation input of the block, elements AND of the second group, the first inputs of which are the corresponding information P1 inputs of the second group of the block, the second inputs are connected to the corresponding outputs of the counter, and the outputs - to the corresponding input The am of the second element, the output of which coeAftHeH with the input of a single vibrator, which is the code of the block, 5. The device is based on riol, one of the following, so that the tag contains a clock and my clock generator, a pepper, the second third and fourth inputs of which are shown; The output signals of the first, second, and third e.pements of And and the trigger, and the output is the output of the timer, the first, second, third, and third L.-Tementon II are, respectively, nepBbp-j, HTopfiiM, and the third pass of the timer, and the second inputs are connected to the outputs of the first 1 of the second second and third accumulative copes, whose inputs are connected to the remote terminal, the R and S inputs of the trigger are the fourth and fifth inputs of the timer, respectively. 6. The device according to claim 1, characterized in that the control unit contains a shift register, the installation input of which is connected with a switch output, a clock input with a generator code, a second code with a control input of a pulse driver, a third output with R-inputs of the first and second triggers, the first and fourth outputs are the first output of the block, and the information input, the generator inputs, delays, S-input of the second trigger and the first input of the second element I are the input of the block, the first input of the first element I is connected to the output of the first trigger, the S-input of which is connected to the output of the delay element, the second inputs of the first and second elements AND under Switched to the generator output connected to the information the input of the pulse former, the outputs of the first and second elements, the course of which is the second output, respectively, the third chet-block, the output of the second flip-flop and twisted and fifth outputs of the block. 9 and .2 YYYY.Z FagC 5 V v v