SU1488845A1 - Device for computation and planning information correction on radar data of moving object - Google Patents

Description

The invention relates to computing and can be used in automated air traffic control systems. The aim of the invention is to increase the capacity of the automated air traffic control system and reduce the load of dispatchers. The device contains a memory block 1, a decision block 2, a control block 3, a timer 4, registers 5, 6, one-shot 7, 8, an adder 9, a block 10 subtraction, a HE element 11, a generator 12 clock pulses. 1 z.p »f-ly, 6 ill.

Output V / h17

Bx75 Bx! B Bx1 ^

4 ^

00

00

00

four*

SL

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3

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The invention relates to computing and can be used in automated air traffic control systems $

(Driving control system) in terms of entering the actual time of flight control points.

The aim of the invention is to increase the capacity of the automated control system of air flow} and reduce the load of dispatchers

Figo 1 is a block diagram of the device; Fig 2 - control unit; Fig 3 is a diagram of a memory block; 15 in FIG. 4, is a double register; FIG 5 - the internal structure of the group of elements OR; Fig 6 is a block diagram of decision making.

The device contains a memory block 1, 20 decision block 2, control block 3, timer 4, registers 5 and 6, one-shot 7 and 8, adder 9, block 10 subtraction, element NO 11, generator 12 clock pulses, output- 25 stroke 13 device synchronization, device coordinate recording input 14, device coordinates 15 and 16 coordinates, device information output 17, communications 18-31, one-shot 32 and 33, shift register 34, AND elements 35 and 36, HE elements 37 and 38, OR element 39, the counter 40, the decoder 41, the input 42 of the shift register 34, the information input 43 of the register 34, the installation input 44 of the counter 40, registers 45 and 46, group of 47 elements OR, shift register 48, element NOT 49, element AND 50, element <

OR 51, input 52 shift register 48, dd information input 53 register 48, registers 54 and 55, elements OR 56, communications 57-59, register 60, subtraction nodes 61 and 62, multiplication nodes 63 and 64, adder 65, register 66 , elements OR 67-70, elements AND 71-73, shift register 74, register 75, comparison circuit 76, group of elements OR 77, input 78 of the group of elements 77, register shift 79, 74, installed.

ab initio register entry 74.

The digit capacity of register 34 is n-1, the digit capacity of register 48 is n + 1, the digit capacity of register is 74-7. The number of two - ^^ input elements OR in the group 77 is equal to the digit capacity of the register 66 "If // // is the capacity of the retistor (adder), then

// 5 // = // 6 // = // 45 // = // 9 // =

= // Yu //,

and

// 54 // = // 55 // = // 61 // =

= ... = // 67 // = 1П5Ц.

Before using the device

senior bits of all shift registers are set to one state, and the rest - to zero. In the counter 40, the code p-2 is set. Code 75 is recorded in register 75. ”1” Registers 45 and 41 (in all but η-x are recorded, according to the actual Loleg plan (FPL), the time of flight of control points (in ascending order) and the corresponding coordinates (X and Y) control points. All other registers are reset. "Timer 4 shows the current time."

The device works as follows.

Once for the review (for example, 10 s) of the radar, the coordinates of the object correlated with the FPL are fed to the inputs 15 and 16 of the device, the calculated part of which is recorded in the registers 45 and 46 of the memory unit 1 ”The output of the coordinates <X _V , Y _& > is accompanied by a single pulse supplied to input 14 of the device. According to this pulse (fig. b), the coordinates <X ₀ , Y _e > are recorded in register 60 and the information OR in register 67 cyclically shifts the information in register 74. At the same time, the logical zero from the eldest (entry 80). In register 74, the code 0100000 is set. The logical zero signal of the first trigger of register 74 through the element NOT 72 will open the element AND 73. The clock pulses of the generator 12 will start at input 20 · enter the input 79 of register 74.

The clock period ’of the following clock pulses is chosen so that the multiplication nodes 63 and 64 have time to complete the required actions.

When the second clock pulse arrives from the generator 12, the nodes 61 and 62 of the subtraction will form at their outputs the difference in coordinates of the object and the mandatory reporting point (AML), the span of which is expected:

HELL ⁼ Χβΐ ^- У0Ι ^- At, I

where X ₆ ; , U _in ; - object coordinates

at the ΐth revolution of the locator; X ,, At <coordinates UNDER. Next clock

five

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the pulse from generator 12 once again shifts the code recorded in register 74 (0010000). The logical unit from the output of the register 74 through the element OR 69 will include the nodes 63 and 64 multiplication, which will carry out the construction of the numbers & _x and d | ^ in the square. Next, the addition operation and on the rear front will be

TO; + C ·,

written in register 66. This value is compared by the circuit 76 comparison with the previous value Κ · _ _1? written in register 75. For the first comparison (when ί = 1), K _o ~ 11.0.1 is assumed. If K;. ,, then the signal from the output of the element OR 70 through the open element And 71 and OR 68 the contents of the register 66 will be overwritten in the register 75, and the output 28 will generate a signal of a logical unit.

If K; > what is meant by the passage of the AML, then at the output 26 a signal of a logical unit will be formed.

When the code 1000000 is set in register 74, the signal of the logical unit from the output of the first digit of the trigger through the element NOT 79 closes the element And 73. Thus, the arrival of the clock pulses at the input 79 of the register 74 will stop.

The signal of the logical unit from the output 28 of block 2 will overwrite the indication of timer 4 into register 5 and the difference is formed at the output of block 10 subtraction

Δ - C -2 ~ T 1 ·

When a signal is received from the logical unit from the output 26 of block 2, this difference will be written to register 6. On the falling edge of the signal from output 26, the one-shot 8 will operate, giving a pulse of logical unit to the input 27 of block 3 (Fig. 2). This pulse will zero the counter 40 and a logical zero signal will be set at the output of the decoder 41, which through the NOT 38 element will open the AND 36 element. The generator 12 signal through the AND 36 element enters the one-shot 32 input, which will generate a short pulse at the output 23 (the duration of which is much less the duration of the pulse generator 12), which will write to the η-th register 45 (Fig. 3) information generated at the output of the adder 9:

ETO = (COP ₂ ) + Δ,

where (COP ₂ ) - the contents of the second register 45;

5 ETO - estimated time of flight

control point.

On the falling edge of the pulse from the output of the AND 36 element, the code is shifted in the register 34. At the exit 10 of 24, a code 10 ... 0 is formed, which enters the input of the group 47 of the OR elements (Fig. 3) and overwrites the information from the third register 45 into second,

15 At the output of the first trigger register 34 (Fig. 2) a logical zero signal will appear that will close the AND 36 element and through the NOT 37 element will open the AND 35 element. Now the pulse 20 from the generator 12 output through the AND 35 and OR 39 elements will shift the code 010 ... 0, written in the register .34. Each shift will result in overwriting (FIG. 3) of the information in registers 45: 4 "*" 3, 5 - * "4, etc. , η (n-1).

After the last shift (Fig. 2) in register 34, the value of the counter 40 will increase by one and the output

30 of the first trigger, the logical unit signal will reappear, which, through the NOT 37 element, closes the AND 35 element and prevents the clock pulses from entering the 42 register 34. However, the same signal will open the AND 36 element and a short pulse will again be generated at the output 23, which will be written in η-th register 45 (Fig. 3) corrected time - ETO for three ~

The 40th control point, the value of which is formed at the output of the adder 9. This procedure will be repeated until the code of numbers is established at the output of the counter 40

45 la (p-2). In this case, a signal of a logical unit will appear at the output of the decoder 41, which will close the element 36 through the element NOT 38. A short pulse will be generated at the output 22 of the single-oscillator 33, which will write (Fig. 6) to the register 75 code 11. 1 and shift the code in register 48 (FIG. 3) through the element OR 51 (input 52).

55

Code 010 ... 0 register 48 (Fig. 3)

will rewrite from 2 to 1 (2- * Ί)

the contents of registers 45 and 46. The signal of a logical unit at the input ^ ele7

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coping NOT 4 9 will open the element AND 50 Pulses from the output of the generator 12 will carry out a sequential shift of the code in register 48, carrying out the following process of rewriting 3 - * - 2, 4 - * - 3, „„ „, п ~ (п-1) information in registers 45 and 46 _O

The signal from the (n + 1) th output of the register 48 'can be used in ka-x. the synchronization value for issuing the next ETO value (output 13).

Thus, the device on the radar information will automatically record the span of the control point and adjust the calculated part of the flight plan, correlated with the object,

Claims (2)

Claim 1 o Pa, respectively, the inputs of the first and second terms of which are connected to the output of the second register and the information output of the memory unit, respectively, the output of the characteristic of which is connected to the output of the device synchronization and to the input of the subtracted subtraction unit, the input decremented. which is connected to the output of the first register, and the output is connected to the information input of the second register, the information input of the first register is connected to the output of the timer. 15 1. A device for calculating and adjusting planned information on radar data of a moving object, containing a memory block, a control unit and an adder, characterized in that, in order to increase the capacity of the automated air traffic control system and reduce dispatcher loading, two registers are entered into it , two one-shot, NOT item, subtraction unit, timer, clock generator and decision block, including registers, AND, .OR, NOT elements, two subtraction nodes, two multiplication nodes, sum the mater, the group of elements OR, the comparison circuit and the shift register, the input of which · hectare is connected to the output of the first element OR, the first input of which and the input of the first register are connected to the input of the recording device coordinates , the first input of which is connected to the output of the NOT element, the input of which is connected to the output of the first digit of the shift register, the outputs of the first register are connected to the inputs of the decreasing first and second subtraction nodes, respectively, the inputs of the subtracted which are the inputs of the device coordinates, the outputs of the first and second subtraction nodes are connected to the inputs of the multipliers of the first and second multiplication nodes, respectively, the outputs of which are connected to the inputs of the first and second terms of the adder, respectively, the output of the adder is connected to the information input of the second. of the left register, the output of which is connected to the first input of the comparison circuit and the first inputs of the elements OR groups, the outputs of which are connected to the information inputs of the third register, the output of which is connected to the second input of the comparison circuit, the outputs of the “More” and “Less”, are connected to the first inputs the second and 'third elements AND respectively, the second inputs of which are connected to the output of the second element OR, the output of the third element OR is connected to the synchronization inputs of the first and second multiplication nodes, the output of the second element AND with one with the first input of the fourth OR element, the output of which is connected to the recording input of the third register, the bits of the shift register, except the first, are connected respectively with the first input of the third OR element, with the recording input of the second register and the second input of the third OR element, the input of the second element OR, with the third input of the third element AND, the second input of the second element OR and the high-order input of the shift register, the second input of the first element AND decision block, the clock inputs of the memory unit and the control unit The devices are connected to the output of the clock generator, the information outputs of the device and the first and second information inputs of the first register of the decision block are connected to the coordinate outputs of the memory block, respectively, the write resolution of the control block is connected to the shift input of the memory block and the second inputs of the fourth OR element and OR group of the decision block, the output of the second element And the decision block through the first one-shot is connected to the input of the first register, the output of the third element And the decision block is connected to the recording input of the second register and through the NOT element to the input of the second one-shot, the output of which is connected to the control input of the control unit, the recording output of which is connected to the recording input of the memory block, the first and second information inputs of which are connected to the information outputs of the block control and summa9 1488845 2. The device according to p. ^ Characterized in that the control unit contains one-shot, elements AND, OR, NOT, shift register, counter and decoder, the input of which 20 is connected to the output of the counter, the installation input of which is the installation input of the block, the output of the decoder through the first the one-shot is connected to the output of the write resolution of the block, and through the first element NOT to the first input of the first element I, the input of the shift of the shift register is connected to the output of the element OR, the output of the first digit of the shift register is connected to the second input of the first element I and h cut the second element NOT to the first input of the second element AND, the output of which is connected to the first input of the OR element, the second input of the second element AND and the third input of the first element AND are connected to the clock input of the block, the output of the first element AND is connected to the second input of the OR element and through the second one-shot - with the output of the block, the outputs of the digits of the shift register, starting with the second, are the inertial output of the block, the output of the last digit is connected to the counting input of the counter and the inertial input of the shift register. FIG. 2 Fi9.3 .