SU1488842A1 - Random signal mean value computer - Google Patents

Description

The invention relates to computing. The aim of the invention is to simplify the device.

and increase its speed. This goal is achieved by the fact that in the known device containing the count of the number of samples 1, the pulse counter 2, the first 4 and second 6 reversible counters, the generator 7 clock pulses, five elements And 812, the first delay element 14, the first control trigger 16 and the element OR 17, the current value counter 3, the adder 5, the second control trigger 13, and the second delay element 15 are introduced. The proposed device reduces the number of elements used and the connections between them and improves the efficiency of digital signal processing. 1 il.

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The invention relates to computer technology and can be used in specialized devices for automatic control, information processing, and in systems for automating scientific research.

The aim of the invention is to simplify the device and increase its speed. YU

The drawing shows the block diagram of the device.

The device contains a counter 1 of the number of samples, a counter 2 pulses, a counter 3 of the current value, a first reversing counter 4, an adder 5, a second reversing counter 6, a generator of 7 clocks, the first, second, third, and fourth elements And 8- 12, the second control 20 trigger 13, the first and second delay elements 14 and 15, the first control trigger 16, the element OR 17.

The operation of the device is based on the implementation of the algorithm. 25

^Ψ "G ^(Υ Ν-, - ^Υ ν) · (1)

When Υ _Ν.,> Υ ^ arithmetic mean in the apparatus is obtained by adding the current value Υ _Ν sample element with the value. which is obtained by a withdrawal of each Ν-th pulse of the pulse sequence corresponding to the difference between the previous average of Uts_ and a current value Υ _Ν sample element that soot30

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the product

γ,) ·

When Υ _Ν > Υ ^., The average is ₄₀

The actual value in the device is obtained by subtracting the value from the current value _{Ν выбор} of the sample element, which is obtained by removing each Νth pulse from the pulse sequence corresponding to the difference between the current value of the sample element and the previous arithmetic average, which corresponds to the product

At the initial moment, after the signal "Set to" 0 ", the number of samples and the pulse counter 2 are filled in the counter 1, the first value is recorded in the current value counter 3, the control trigger 13 and '16' are in the zero state. At the output of the device (direct outputs reverse counter 4) will be a zero value. "1" appears at the transfer output of the adder, and the value Υ -1 at the output of the adder,

At the moment when the signal arrives at the device launch input, the trigger pulse switches the second control trigger 13 to the state "1" and the clock pulses from the generator 7 through the element 8. 8. Start to flow to the counter input of the pulse counter 2 and to the input of the delay element 15, in the counter 1 samples, the value Ν-1 is written, the current value from the output of counter 3 is rewritten in the reversible counter 4, and the number from the output of the totalizer is rewritten in the reversible counter 6

Counters 1 samples and 2 pulses together with elements of II II and 10 or And 12 and 9 and the delay element 15 represent the frequency divider of the pulses coming from the output of the delay element 15 to the addition input through elements 12 and 9 or the input of subtraction through elements 11 and 10 reversing counter 4.

Frequency division is in proportion

p = 1Ί to exit N '

by removing each Νth pulse from a sequence of pulses arriving at the direct input of an AND 9 or 10 o element

From the output of the delay element 15, the clock pulses flow through the elements 12 and 9 to the input of the addition of reversible counters 4 and 6 or through the elements 11 and 10 to the inputs of the subtraction of reversible counters 4 and 6. Control of the operation of the elements 12 and 9 and 10 by means of an adder 5 and the first control trigger 16, which enable the passage of pulses either through elements I _: 12 and 9, or through elements 11 and 10 depending on the ratio of the value Υ _Ν of the sample element and the previous average arithmetic value _Ν _ ,

When Υ _Ν > Υν-Ί ^{on the} code of the transfer signal of the adder 5, "1" appears and the first control trigger 16 switches to the state "1". When this clock pulses pass through the elements And 11 and 10 to the inputs of the subtraction

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first 4 and second 6 reversible counters. When <Υ _Η ., At the output of the transfer signal of the adder 5 - the signal "O", the first control trigger 16 is in the zero state. When this clock pulses pass through the elements And 12 and 9 to the inputs of the addition of the first 4 and second 6 reversible counters. As a result, in accordance with expression (1), the current value Υ _{Ν is} added to the current value recorded in the first reversible counter 4 or the module of the number is subtracted from it

[(Υ _ν ., - Υ _ν ) (Ν-1) / ν |, 15

Upon receipt at the input of the subtraction or the input of the addition of the second reversible counter 6 of the required number of pulses equal to the modulus of the difference (-μ-, - Υ _Ν ^, the output of the overflow 20

or the output of the zeroing of the counter 6, a pulse will appear that will translate the first 16 and second 13 control triggers to the zero state and the device enters the ready state. On the 25th output of the device (direct outputs of the reversible counter 4) there will be an arithmetic average value. After a period of time determined by the first delay element 14, the pulse is re-. 30 refills or zeroing from the output of the counter 6 is fed to the device start input. After this, subsequent samples are processed similarly. . ₃₅

Claims (1)

Claim A device for calculating the average value of a random signal - containing a counter for the number of samples, a pulse count counter, first and second reversible counters, a clock pulse generator, five AND elements, the first 'delay element, the first trigger and the OR element, and the counting input of the counter the samples is the start-up device input, the output of the first element I is connected to the addition input of the first reversible counter, the input of which subtraction is connected to the output of the second element I, the output of the third element I connected to the input is subtracted I am the second reversible counter, the addition input of which is connected to the output of the fourth element I, the first input of which is connected to the inverse output of the first trigger, the output of the clock generator is connected to the first input of the fifth element I, characterized in that, in order to improve performance, it is entered the current value counter, the adder, the second trigger and the second delay element, while the inverted outputs of the counter of the number of samples are connected to the corresponding information inputs of the pulse counter, the transfer output of which It is connected to the inverse inputs of the first and second elements I and to the input of a parallel recording of the pulse counter, the counting input of the pulse counter is connected to the input of the second delay element and the output of the fifth element I, the information input of the device is the counting input of the current value counter, the outputs of which are connected respectively to information inputs of the first reversible counter and to the inputs of the first addend adder, the inputs of the second addend of which are connected to inverse outputs of the first reversible counter The parallel recording input of which is combined with the parallel recording input of the second reversible counter, with the installation input in "1" of the second trigger, with the output of the first delay element, which is connected via the wiring OR circuit to the device startup input to the corresponding the outputs of the adder, the transfer signal of which is connected to the inverted output of the first trigger, the transfer output of the adder is connected to the input of the first trigger in the "1", the first input of the element OR connected to the transfer output of the second reversible counter, the reset output of which is connected to the second input of the OR element, the direct input of the first element AND is connected to the addition input of the second reversible counter, the input of which subtraction is connected to the direct input of the second element And, the second input of the fifth element And connected to the direct the output of the second trigger, the output of the second delay element connected to the second inputs of the third and fourth elements And the first input of the third element And is connected to the direct output of the first trigger, the output element And LI is connected to the inputs of the installation in ”0” of the first and second triggers and to the input of the first delay element ”