SU1487090A1 - Data receiver - Google Patents

Description

The invention relates to the transmission of discrete information and can be used in telecontrol systems and in communication systems with feedback. The purpose of the invention is to increase the reliability of receiving information. The device contains a memory block 1, a control unit 2, a switch 3, a control signal generator 4, six AND 5-10 elements, three OR 11-113 elements, and five triggers 14-18. The invention allows to increase the reliability of receiving discrete information without increasing the memory capacity of the device. 2 Il.

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The invention relates to the transmission of discrete information and can be used both in telecontrol systems and communication systems with feedback.

The purpose of the invention is to increase the reliability of receiving information.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - time diagram of his work.

The device contains a memory block 1, a control block 2, a switch 3, a control signal generator 4, the first, second, third, fourth, fifth and sixth elements AND 5-10, the first, second and third elements OR 11-13, the first, second, the third, fourth and fifth triggers 14-18, input 19 of the receiving channel of the device, output 20 of the return channel of the device, clock input 21 of the device.

The device works as follows.

The incoming information to the input of the direct channel of the device. consistently moving from memory block 1.1 to large memory blocks. Prior to the control of blocks 1.K '1, I and I. The memory under the action of the preceding pulse of control block 2 triggers 14-16 are set to a state in which logical zeros occur on the direct outputs of the triggers and logical units on the inverse outputs. The signals of the logical unit from the inverse output of the trigger 14 through the element OR 12 and from the inverse output of the trigger 15 directly set the triggers 17 and 18 to a state in which the inverse outputs of the triggers 17 and 18 contain signals of the logical unit.

As soon as the discrete information starts to fill the control block Ι.Κ of memory (Fig. 2a), the trigger 14 overturns, and on the direct trigger of the trigger 14 a signal of the logical unit will appear (Fig. 2b), which through the Ibi elements OR 11 will go to the first inputs of the elements Both 9 and 10. Since the trigger 18 has not yet changed its state (Fig. 2d), then at the second input element AND 9 there is also a signal of a logical unit, which through the element OR 13 and elements 5 also affects generator 4 of the control signal (FIG. 2c>). The clock pulse forming the second character of the code combination, through the open element And 10, overturns the trigger 18, as a result of which the elements 9 and 10 will close (Fig. 2). At the output of the element OR 12 an impulse is formed, indicating the presence of information in the control block .Κ of memory.

As long as there is no information in the control block Ι.Κ, there is no signal at the output of the device 20, since And 8 and 9 are closed. Appearance

code combination in the control block 1.1. memory opens element 8 and forms a pulse at the input of generator 4 according to the algorithm described above, using triggers 15 and 17, elements 7 and 8, and element OR 13. At the same time, under the action of the generated pulse at the output of element 8, through the element OR 12 is triggered trigger 18 to its original state.

When filling with the code combination of the control block 1.t of memory, trigger 16 overturns and the signal of the logical unit through the element OR 11 enters the first inputs of the elements AND 9 and 10, which allows you to generate another pulse at the second input of the element 7, using for this purpose the triggers 16 and 18 , elements AND 9 and 10 and elements OR 11 and 13.

Having received the first control signal formed from the memory control block Ι.Κ, the forward channel station changes the mode of operation of its transmitter (for example, increasing the output power) until the signal generated from the control memory block 1.1, then changes the mode again (again increasing input power) of the operation of the transmitter of the direct channel before the arrival of the signal formed from the control unit 1.t memory, etc. If the signal from the control units 1.1 and 1.t memory is missing, then the operation mode of the transmitter of the direct channel set navlivaet the original. The expected time of arrival of the control signal is easily determined.

Thus, the invention allows to increase the reliability of receiving discrete information without increasing the memory capacity of the device.

Claims (1)

Claim A device for receiving signals containing a memory block whose input is the input of the device, the first, second and third control outputs of the memory block are connected to the first, second and third control inputs of the control unit, respectively, the first output of which is connected to the first input of the switch, the second output of the control unit connected to the first input element And, the output of which through the control signal generator is connected to the second input of the switch, the output of which is the output of the device, characterized in that increase the reliability of reception of signals, it introduced the first, second, third, fourth and fifth triggers, second, third, fourth, fifth and sixth elements AND, first, second and third elements OR, the third output of the control unit is connected to the combined, inputs "Reset »First, second and third 1487090 five flip-flops, the fourth, fifth and sixth control outputs of the memory block are connected to the “Installation” inputs of the first, second and third flip-flops, respectively, the direct output of the first trigger is connected to the first input of the second element AND whose output ^{5 is} connected to the first input of the first element OR, direct output the second trigger is connected to the combined first inputs of the third and fourth elements And, the direct output of the third trigger is connected to the second input of the first element OR, the output of which is connected to the combined first inputs of the fifth and the sixth And elements, the inverse output of the first trigger is connected to the first input of the second element OR, the inverse output of the second trigger is connected to the second input of the second element And to the "Reset" input of the fourth trigger And, the second inputs of the third and sixth elements And are combined and are tact6 the device’s input, the outputs of the third and sixth And elements are connected to the “Installation” inputs of the fourth and fifth triggers, respectively, the inverse output of the fourth trigger is connected to the third input of the third And element, and to the second input of the fourth And element, the output of which is connected to the first input of the third element OR and to the second input of the second element OR, whose output is under 10 keys to the input "Reset" of the fifth trigger, the inverse output of which is connected to the third input of the sixth element And, and to the second input of the fifth element And, output to orogo connected to the second input of the third OR Eleja ment whose output is connected to the second input of the first AND gate, the first, second, third, fourth, fifth and sixth data outputs are the outputs of the memory block groups unit outputs. 20 o) code combination e) Clock pulses 4) The first trigger output 74 FIG. g d) Inverse output "trigger 78 __ e) exit 'device 20_