SU1487090A1 - DEVICE FOR RECEPTION OF SIGNALS - Google Patents

Description

The invention relates to the transmission of discrete information and can be used in telecontrol systems and in feedback communication systems. The purpose of the invention is to increase the reliability of information reception. The device comprises a memory unit 1, a control unit 2, a switch 3, a control signal generator 4, six AND elements 5-10, three OR elements 11-13 and five triggers 14-18. The invention makes it possible to increase the reliability of discrete information reception without increasing the memory capacity of the device. 2 fig.

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The invention relates to the transmission of discrete information and can be used both in remote control systems and in communication systems with feedback.

The purpose of the invention is to increase the reliability of information reception.

Fig. 1 shows the functional diagram of the proposed device; Fig. 2 shows the timing diagram of its operation.

The device contains a memory unit 1, a control unit 2, a switch 3, a control signal generator 4, first, second, third, fourth, fifth and sixth AND elements 5-10, first, second and third OR elements 11-13, first, second, third, fourth and fifth triggers 14-18, an input 19 of the receiving channel of the device, an output 20 of the reverse channel of the device, a clock input 21 of the device.

The device works as follows.

Information arriving at the input of the direct channel of the device is sequentially advanced from memory block 1.1 to memory blocks with higher numbers. Before the start of monitoring memory blocks 1.K '1, I and I.t, under the action of the preceding pulse of control block 2, triggers 14-16 are set to a state in which logical zeros are present at the direct outputs of the triggers, and logical ones at the inverse outputs. Logical one signals from the inverse output of trigger 14 through OR element 12 and from the inverse output of trigger 15 directly set triggers 17 and 18 to a state in which logical one signals are present at the inverse outputs of triggers 17 and 18.

As soon as the discrete information begins to fill the control block IK of the memory (Fig. 2a), the trigger 14 will flip-flop, and a logical one signal will appear on the direct input of the trigger 14 (Fig. 2c), which will go through the I1 and OR elements 11 to the first inputs of the AND elements 9 and 10. Since the trigger 18 has not yet changed its state (Fig. 2d), a logical one signal is also present at the second input, the AND element 9, which, through the OR element 13 and the AND elements 5, acts on the control signal generator 4 (Fig. 2c>). The clock pulse, which forms the second symbol of the code combination, through the open AND element 10 flip-flops the trigger 18, as a result of which the AND elements 9 and 10 will close (Fig. 2). A pulse will be formed at the output of the OR element 12, indicating the presence of information in the control block IK of the memory.

Until there is no information in the control block I.K., there is no memory signal at the output 20 of the device, since the elements I 8 and 9 are closed. The appearance

The code combination in the control block 1.1. of the memory opens the AND element 8 and forms a pulse at the input of the generator 4 according to the algorithm described above, using triggers 15 and 17, AND elements 7 and 8 and the OR element 13. At the same time, under the action of this pulse being formed at the output of the AND element 8, through the OR element 12, the trigger 18 is reset to its original state.

When the control block 1.t memory is filled with a code combination, trigger 16 flips over and the logical one signal through the OR element 11 goes to the first inputs of AND elements 9 and 10, which allows the next pulse to be generated at the second input of AND element 7, using triggers 16 and 18, AND elements 9 and 10 and OR elements 11 and 13 for this.

Upon receiving the first control signal generated by memory control unit 1.K, the forward channel station changes its transmitter operating mode (for example, by increasing the output power) until a signal from memory control unit 1.1 arrives. It then changes the forward channel transmitter operating mode again (by increasing the input power once again) until a signal from memory control unit 1.t arrives, and so on. If the signal from memory control units 1.1 and 1.t is absent, the forward channel transmitter operates at the initial mode. The expected arrival time of the control signal is easily determined.

Thus, the proposed invention makes it possible to increase the reliability of receiving discrete information without increasing the memory capacity of the device.

Claims (1)

Claim A device for receiving signals containing a memory block whose input is the input of the device, the first, second and third control outputs of the memory block are connected to the first, second and third control inputs of the control unit, respectively, the first output of which is connected to the first input of the switch, the second output of the control unit connected to the first input element And, the output of which through the control signal generator is connected to the second input of the switch, the output of which is the output of the device, characterized in that increase the reliability of reception of signals, it introduced the first, second, third, fourth and fifth triggers, second, third, fourth, fifth and sixth elements AND, first, second and third elements OR, the third output of the control unit is connected to the combined, inputs "Reset »First, second and third 1487090 five flip-flops, the fourth, fifth and sixth control outputs of the memory block are connected to the “Installation” inputs of the first, second and third flip-flops, respectively, the direct output of the first trigger is connected to the first input of the second element AND whose output ^{5 is} connected to the first input of the first element OR, direct output the second trigger is connected to the combined first inputs of the third and fourth elements And, the direct output of the third trigger is connected to the second input of the first element OR, the output of which is connected to the combined first inputs of the fifth and the sixth And elements, the inverse output of the first trigger is connected to the first input of the second element OR, the inverse output of the second trigger is connected to the second input of the second element And to the "Reset" input of the fourth trigger And, the second inputs of the third and sixth elements And are combined and are tact6 the device’s input, the outputs of the third and sixth And elements are connected to the “Installation” inputs of the fourth and fifth triggers, respectively, the inverse output of the fourth trigger is connected to the third input of the third And element, and to the second input of the fourth And element, the output of which is connected to the first input of the third element OR and to the second input of the second element OR, whose output is under 10 keys to the input "Reset" of the fifth trigger, the inverse output of which is connected to the third input of the sixth element And, and to the second input of the fifth element And, output to orogo connected to the second input of the third OR Eleja ment whose output is connected to the second input of the first AND gate, the first, second, third, fourth, fifth and sixth data outputs are the outputs of the memory block groups unit outputs. 20 o) code combination e) Clock pulses 4) The first trigger output 74 FIG. g d) Inverse output "trigger 78 __ e) exit 'device 20_