SU1485405A1 - Logarithmic converter - Google Patents

Description

The invention relates to devices for converting the analog form of information into digital with logarithmic and computer technology. The invention allows to reduce the conversion error and expand functionality. This is achieved by the fact that the device of the exponential voltage, containing the source 2 of the reference voltage, the comparator 6, the generator 5, entered switches 3, 4, triggers 9, 10, counters 2, 3, registers 14, 19, the comparator 21, digital comparator 16, differential amplifier 20, integrator 17, shaper 8 short pulse, element 7, synchronization unit 11, frequency divider 18,

Analog -> Pulse and Code Communications

logical connections

, sf f _ig

but

3

1485405

four

The invention relates to devices for converting the analog form of information into digital with logarithm and can be used in automation, measurement, conversion, and computer technology.

The aim of the invention is to reduce the conversion error and the expansion of functional capabilities.

FIG. 1 shows a functional diagram of the converter; in fig. 2 timing diagrams of the converter; in fig. 3 - functional 15 scheme of the exponential voltage generator; in fig. 4 - timing diagram of the exponential voltage generator.

The device contains an input bus 1.20 1, source 2 reference voltages, switches 3 and 4, generator 5 exponential voltage, comparator 6, element 7, shaper 8 short pulse, triggers 9 and 10, block 1 G 25 synchronization, counters 12 and 13, reg 14, reference frequency generator 15, digital comparator 16, integrator 17, frequency divider 18, register 19, differential amplifier 20, 30

comparators 21 and 22, transfer output 23, loan output 24. _

FIG. 2 diagram 25 depicts the * pulse recording information in registers 14 and 19; diagram 26 — sync pulse 35 — generator 5 synchronization; diagram 27 — impulse of installation of counters 12 and 13 V ”0"; diagram 28 — generator output voltage 5; diagram 29 — voltage at the output of switch 40; diagram 30 — output voltage of the comparator 6; diagram 31, signal at the output of element 7; Chart 32 is the signal at the high-order output of the counter 13, Chart 33 - 45

the signal at the inverting output of the thrigger ^is 10; diagram 34 is the signal at the output of switch 3; diagram 35 - signal at the direct output of the 11-flip-flop 9; diagram 36 - impulse on you -. ^ θ xbde driver 8; diagram 37: the number of pulses counted by counter 13; Diagram 38 is the same for counter 12. Time points: T1 is the beginning of the synchronization pulse of the generator of the exponential voltage;

T2, T9 - the moment of resetting the counters to "0" and installing the ϋ-flip-flops: ϋ-flip-flop 10 to "0", ϋ-flip-flop 9 to "1",

the moment of connection of the first reference voltage and _{o (} - the beginning of the formation of the exponential voltage; TZ the beginning of the measurement T _c and the calibration T _for the time intervals; T4 - the moment of connection of the measured voltage and _x ; T5 - the end of the measuring T _c time interval;

TB - the moment of connection of the second reference voltage and _og ; T7 - the end of the calibration T * time interval; T8 - the moment of rewriting digital information from the counters to the registers.

The generator 5 (Fig. 3) contains capacitors 39 and 40, resistors 41 and 42, diodes 43 and 44, voltage follower 45, analog adder 46, resistor optocoupler 47, generator output 48, control input 49, synchronization input 50.

FIG. 4, the numbering of the diagrams 26. and 28 coincides with the numbering of the same diagrams shown in FIG. 20 _> besides ^ diagram 51 is the voltage at the first input of the analog adder 46; diagram 52 is the voltage at the output of the analog adder 46.

The Converter operates as follows.

In the time interval between the T1 and T2 moments, the capacitor 40 is charged through the analog adder 46 and diode 44 by pulse 26 from the second output of block 11, and after this pulse from the moment T2 begins, the formation of exponential voltage 28 begins. : first in "1" second in "O" if they were in other than the specified conditions (for example, immediately after power-up), and setting the counters to "0".

Thus, from time T2, the first channels of switches 3 and 4 are connected so that the output of switch 3 is “Log. G”, the output of the second switch 4 is the first reference voltage ϋ ₀ , and at the output of comparator 6 “Log. O”. At the moment of the TZ, the exponential voltage 28 becomes less than the reference voltage and _{0 (} a positive differential is formed at the output of the comparator 6, which, acting on the inputs of the три-flip-flops, causes them to overturn. At the direct output of the ϋ-flip-flop 9, the formation of the measuring time interval T _and , and on the inverse trigger output 10 - cali

1485405

rovovochnogo interval T _to . The counting of counters 12 and 13 begins. After overturning of the S-flip-flop 10, the signal from its inverse output, acting on the corresponding inputs of switches 3 and 4, causes both switches to switch to the second channels in such a way. at the ϋ-input of the ϋ-trigger 9 "Log.

"0", the measured voltage and _{x are} connected to the input of the comparator 6, and υ _χ Ζ. And ₀ , so that at the time T4 the comparator 6 again goes to '? 0 ".

At time T5, the exponential voltage 28 becomes less than measurable 15 and _x , comparator 6 generates a second positive differential, which leads to tilting of the ϋ-flip-flop 9 to the initial state, and the formation of the measuring interval ends. Its duration is equal to T _{1 {} =

= T5-TZ.

For the points in time TZ and T5, the ratios are obvious.

25

- (Lt _r y / S,

and ₀ , = M, (O

(Tu-t _g ) / &

and _x = and ₉ C _; (2)

where and ₀ - the first reference voltage; and _x - measured voltage; and _? - exponential value

voltage at the time of 35 and T2;

- time constant of exponential voltage.

After dividing (1) and (2) th logarithm, we get ⁴ θ

A logical 'Ί "appears. Acting on the inputs of switches 3 and 4, it causes them to switch to the third channel and a second reference voltage is connected to comparator 6. Comparator 6 changes to" 0. "This scheme prepares for fixing the end of the calibration interval.

Thus, the measurement range ϋ _and is determined by the bit depth η of the counter 13 and the required resolution Δ, dB:

At time T7, the exponential voltage 28 becomes less than the second reference voltage ϋ ₀₂ , the comparator 6 generates another, third positive differential, which leads to the tilting of the ϋ-flip-flop 10 (as the signal at its ϋ-input changes in m Tb moment). At the inverse output of the 13 trigger 10 ends forming

niya gauge interval, which the can calculate by analogies with (one) - (3) ^t to 1n and _{0 [} , ^and ' (five)

This interval is converted to code by a second counter so that its output code

to op to op

ΐη

e and _o2

(6)

4- ^ 1 "^ · (3)

^and 02.

Interval T _and converted to code. the first counter so that its output code

К „- ^Е о» Л 1п ^ £. (four)

ϋ-trigger 10 at time T5 does not work, because a logical “0” acts on its information input, starting from time T2 and up to time TB. At time TB at the output of the senior discharge of the counter 13

By a set of blocks 10, 13, 16, 19, 20, 17, 5 this code is maintained equal to the nominal

Ν _Κ = Ν _ΚΟ (7)

with an error not exceeding the unit of account, since the comparison is carried out in digital form by a digital comparator 16.

Thus, the time constant, the exponent with the accuracy of the unit of account is maintained equal to the value determined from (6) with (7)

to

(eight)

^£ ° n ^1p and *

Ί

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eight

Substituting the value of c7 _? from (8) to (4), we obtain

1n

de

Ν _Μ = Ν _κο

about"

(9)

Equality (9) can be written in vi, θ

20 1 ₈

Tschsch.

20 ι ₈

(ten)

15

“

Pipeline simultaneously with the D-flip-flop 10 at time T7 and the measuring interval becomes equal to the gauge T = T _{& K.} At the same time, the output code of the logarithmic ADC Ν „= is the criterion for the performance of the entire device.

As can be seen from (9), the conversion error is determined by the errors of the installation of the reference voltages bai ₀₁ ... the offset voltage of the comparator and _cm and the unit of account.

The exact calculation by the formula (9) is quite complicated. However, if you meet the conditions

From (10) it can be seen that the output code of the logarithmic converter is proportional to the logarithm of the ratio of the measured and reference voltages.

With an increase (during transients at power up), the calibration interval is bounded above by the value of T9-TZ pulse 27 of the ϋ-flip-flop preset. When excessive decrease £ ₉ below a certain value (this case is marked in figure 28 in phantom) the third rising edge at the output of the comparator is absent (broken line in figure 30), therefore the calibration interval T _to limited below pulse 36 output from the generator 8 via element 7 in order to eliminate the inversion of the sign of feedback on the chain of adjustment

The presence in the scheme of the second 21 and third 22 comparators that perform logical functions

20

25

thirty

35

40

^υ ^ υ ,, ρ;

45

accordingly, it allows using the device as part of a wide-range logarithmic ADC.

Operational verification of the operability of the logarithmic converter is carried out by removing the input voltage.

I

As can be seen from the time diagrams 30 and 31, there is no positive difference at time T5, and the output voltage of element 7 (diagram 31) is zero up to time T7, i.e. The ϋ-flip-flop 9 of the slave20 1 ₆ - ^υ .0Α ..- ⁺ -ξ. ^ .. · ⁺ ·. · ^ .. ^υ Ρ-? <A · ^and o <

20 1 ₈ AP01 _d

(AND)

the resulting error does not exceed a few counts D .. As for the formation of the measurement of T _m and T _c of the calibration interval uses the same comparator, the conditions (11) is facilitated.

In expression (11), the error associated with the inaccuracy of the formation of the exponent by the generator 5 is not taken into account. The generator of the exponent works as follows. The capacitor 40 is charged by the synchronization pulse 26 and then discharged through a chain of resistors 41 and 42 and an optocoupler resistor 47. The error in the formation of the exponent 28 is caused by three factors: leakage current ΐ ^ _{τ of} diode 44, input current of the comparator 6 (fig • 1) ΐ in and change in capacitance diode 44 DSDs in the process of exponent formation. Element base allows you to implement

20 1 ₆ (1 + 4 (3 - 5) b

^ min

where “minimum current capacity

40 within the working area of the exponent (T2-T8 interval).

In addition, it is necessary .Vypolnit

20 1§ (1 +

WITH,

9 1485405 ^'10

The fulfillment of the latter condition is provided in the scheme (FIG. 3) "nodes 45,

39, 43 and 46.

I

five

The output voltage of the generator 5 through the repeater 45 and the level binding circuit containing the diode 43 and the capacitor 39 is fed to the first input of the analog adder 46, thanks to which during the formation of the working section the exponents are provided

—Y 0.

When choosing the parameters of the logarithmic ADC, it should be noted that the value of the code _{κ κο} is determined by the range of 20 'reference voltages

Tso,

and

02

(12)

25

and the required resolution

BUT

Ν _κο

thirty

(13)

and the time constant of the exponent is related to the reference frequency by the ratio 35 (8), which, taking into account (12) and (13), gives

20 18 1

(14) 40

The value Ζ determines the speed of the converter, the conversion time

^π Ρ ~ Δίοη '

" 50

Practically, with a reference frequency of several megahertz and the required resolution, for example, A = 0.01 dB, the speed in fractions of milliseconds and the error not exceeding hundredths of a decibel are achievable.

The division factor for divider 18 should be chosen from the ratio

As switches 3 and 4, for example, a dual four-channel analog multiplexer can be used. The synchronization unit can be made in the form of a 10-divider counter with a decoder. The second register can be made in the form of a pair of triggers.

Digital comparator 16 is a 12-bit digital comparator. Two outputs of the comparator are used <3 _{d in} and 9d, ₆ · Thus, while the current counter code is 13

N, ·} - N _κθ output () _{d <6,} the comparator 16 there is a logic "1", then when the N ^ = Ν _Κο, at both outputs circuit 16 logic "0", and when> ^Ν κο, ^on the output is a logical "1" at the output

logical "0".

After termination of the counting by the counter 13 at the time T7, the code Ν _{κ is} set at its output, and at the first and second outputs of the comparator 16, the corresponding variables depending on the ratio of the values Ν «and _Κο . These two bits are written in two-bit: · register 19 on the front of the pulse 25 at time T8 (Fig. 2). The outputs of the register are fed to the differential amplifier 20. The output voltage of the differential-potential amplifier 20 can take on three values: + Е _П ; 0; -E ^. Thus, digital information from the output of the comparator 16 is converted to analog using a simple DAC, including circuits 19 and 20.

After the formation of the calibration interval 33 (Fig. 2), the codes at the outputs of counters 12 and 13 (Fig. 1) do not change until the counters are reset at time T9 (T2) and are equal to: at the output of counter 12 (Fig. 1) Ν _η , at the output of the counter 13 Ν *. From T7 to T8 (Fig. 2), the first and second outputs of the digital comparator 16 (Fig. 1) establish the result of comparing the code with the reference one in accordance with the table.

At the time of T8, information is recorded in registers 14 and 19. and in register 14, the code Ν _η is written, i.e. update conversion result. Register 19 writes the result

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12

comparison (table) $ which is stored for one period of exponential voltage. Thus, further resetting the counter to $ 13, changing its output code in the counting process does not change the state of register 19 to the next write pulse 25 (Fig. 2), Differential Amplifier 20 converts the result, θ

comparison in accordance with the table, where E _l - the supply voltage of the register 19. The transfer coefficient of the differential amplifier is close to unity.

Thus, a set of blocks 15 16, 19 and 20 forms a relay characteristic! differential amplifier output 20

-E _p if N _to > Ν _κο ; 20

0 if N _к = Ν _Ηο ;

* · _Η , if N _к <N _Ko .

25

The dead zone is equal to the unit of account. The integrator 17 continuously integrates the output voltage of the differential amplifier 20. In; tracking output voltage integra-; 30 rator positive. ^!

I 1

During operation of the device, the generator time constant, the amplitude of the exponent, etc. may vary. :

The system works through these changes, 35 while maintaining a constant T _k interval. This may change the camping position interval T with respect _{to the} beginning of the falling portion (moment T2), the exponent, but this does not affect the normal operation 40 the device, as the value of the interval T is selected approximately half exponential period.

45

Claims (2)

Claim 1. A logarithmic converter containing a source of reference voltages, the first and second comparators, an exponential voltage generator, the output of which is connected to the first input of the first comparator, characterized in that, in order to reduce the conversion error 55 and extend the functionality, two три-flip-flops, two counters, two registers, reference frequency generator, digital comparator, differential amplifier, integrator, frequency divider, synchronization unit, short pulse shaper, I element, third comparator, two switches, the first input of the first switch is a bus of a logical unit, the second, third and fourth inputs are combined and are a logical zero bus, the fifth input is combined with the first input of the second switch, the resolution enable input of the first counter and connected to the inverse output of the first 15 flip-flop, the sixth input is combined with the second input of the second switch, the input of the driver is short pulse, ϋ-input of the first три-flip-flop,>> the high-order input of the first group of information inputs of the digital compdrator and connected to the high-level output of the first counter, the remaining bits of which are bitwise connected with the corresponding inputs of the first group of information inputs of the digital comparator, the second group of information inputs which is a bus code, the first and second outputs of the digital comparator are connected respectively to the first and second information inputs of the first register, the entry of which is about edinen a second register write input and is connected to the first output of the synchronization unit, the first and second outputs of the first register are connected co. responsibly with the first and second inputs of the differential amplifier, the output of which through the integrator is connected to the control input of the exponential voltage generator, the synchronization input of which is connected to the second output of the synchronization unit, the third output of which is connected to the installation inputs to "0" of the first and second counters, '8- the input of the first I) -trigger and K-input of the second ϋ-flip-flop, the input of the synchronization unit through the frequency divider is combined with the counting inputs of the first and second counters and connected to the output of the generator of the reference hour The outputs, outputs of the second counter, are digitally connected to the information inputs of the second register, the outputs of which are output buses, the counting enable input of the second counter is connected to the direct output of the second 15-flip-flop, the C-input of which is combined with the C-input of the first три-flip-flop and connected to the output element and the first input 13 1485405 14 which is connected to the output of the short pulse shaper, the second input is connected to the output of the first comparator, the second input of which is connected to the output of the second switch, the third input of which is combined with the first input of the second comparator and connected to the first output of the reference voltage source; the fourth input is combined with the second input of the second comparator, the first input of the third comparator and is the input bus; the fifth and sixth inputs are combined with the second input of the third the comparator and 15 are connected to the second output of the reference voltage source; the outputs of the second and third comparators are, respectively, the first and second buses of the control of the excess of the reference signal,-input 20 of the second три-flip-flop is connected to the output of the first switch. 2. Converter π; 1, characterized in that the generator of exponential voltage is made on the voltage follower, analog adder, two diodes, a resistor optocoupler, two resistors, two capacitors, the first output of the first capacitor is connected to the output of the voltage follower, and the second output is connected to the first input of the analog adder and the anode of the first diode, the first output of the second capacitor, the first outputs of the first and second resistors, the cathode of the second diode and the input of the voltage follower are combined and are the generator output, the first output of the resistor optocoupler is the control input of the generator, the second output of the resistor optocoupler with The second input of the analog adder is the sync synchronization input of the generator, the cathode of the first diode, the third and fourth outputs of the resistor optocoupler, the second outputs of the second resistor and the second capacitor are combined and are the bus of the Zero potential, the output of the analog adder is connected to the anode second diode. I The first Second Ratio Output output Output Ν ^, Ν _{Κο codes} differential amplifier voltage 20 Log "0" Log "0" "to = Νκο 0 Log "0" Log And | II "to “To + Ε Log II 1 II Log ΙΙθΙ! "TO > “To -Ε 1485405 FIG. ϊ 1485405