GB2120481A

GB2120481A - Improvements in or relating to analogue to digital converters

Info

Publication number: GB2120481A
Application number: GB08311045A
Authority: GB
Inventors: Keith Lawson Kimber
Original assignee: COMARK ELECTRONICS Ltd
Current assignee: COMARK ELECTRONICS Ltd
Priority date: 1982-04-23
Filing date: 1983-04-22
Publication date: 1983-11-30
Also published as: GB8311045D0; GB2120481B

Abstract

A dual ramp analogue to digital converter of the type which gates and counts pulses N1, N sequentially corresponding to an input voltage Vin and a reference voltage V ref stored on a capacitor Cr is used with a non- linear transducer. The converter compensates for the non-linearity by means of components Rr*, (R'r, A, fig. 12 not shown) connected in series with the reference capacitor Cr and R2* (R2) connected in parallel with a feedback capacitor C1 of the integrator 10. <IMAGE>

Description

SPECIFICATION Improvements in or relating to analogue to digital converters The present invention relates in general to analogue to digital converters and more particularly to adapted dual-slope converters for use with digital measuring instruments.

In measuring applications, it is sometimes difficult to convert a parameter to be measured into an accurate digital readout due to non-linearity of a transducer providing an analogue voltage to a dualslope analogue to digital converter. One application of many is in measuring temperature with a type K thermocouple as a transducer. Prior art techniques to compensate for this problem suffer certain disadvantages and a general object of the present invention is to provide an improved converter.

According to the present invention an analogue to digital converter employs integrating means for integrating an input voltage derived from a parameter sensed by a transducer with a non-linear response, control means which gates clock pulses providing a digital output and controls switches which connect the integrating means to the input voltage to be measured and to a dynamic reference voltage source provided by a reference capacitor which stores the reference voltage during one phase of operation determined by the control means and the switches and resistance compensating means which constrains the integrating means to provide a response which is substantial linear with respect to the parameter.

The compensating means may take the form of one or more selected value resistors or equivalent resistance means. The value of the or each resistor can be calculated from a mathematical relationship set forth hereinafter. One such resistor can be connected in parallel with a feedback loop or capacitor of an amplifier serving as the integrating means. Another such resistor can be connected in series with the reference capacitor providing the dynamic reference voltage and more particularly between a terminal which receives the input voltage and the plate of the reference capacitor which accepts the reference voltage.In a preferred arrangement the converter comprises an operational amplifier with capacitive feedback forming an integrating means, switching means for selectively connecting the input of the integrating means to a voltage source derived from a transducer sensing a parameter and to a reference capacitor which stores a reference voltage, control means for controlling the switching means and for gating a sequence of digital pulses having a pre-determined relationship with the source of voltage and capable of producing a corresponding digital read out: wherein additional resistors or the equivalent are connected serially to the reference capacitor and across the capacitive feedback of the operational amplifier and these resistors have values adapted to constrain the integrating means to adopt a transfer response to compensate for non-linearity in the source voltage.

As is known, the control means gates clock pulses providing a digital readout and controls the switches which connect the integrating means to the input voltage to be measured e.g. the transducer output, and to the dynamic reference voltage. Thus during one phase or mode of operation the control means would cause the input voltage to be connected to the integrating means for a fixed time interval while the resulting digital output is counted. Thereafter in another phase or mode of operation the control means would connect the voltage stored by the reference capacitor to the integrating means to bring the output thereof back to a pre-determined value, usually zero, in the period determined by the magnitude of the input voltage.In contrast to a known converter operating in this manner the constraining means causes the output of the integrating means to vary in a non-linear manner with respect to time.

The invention may be understood more readily, and various other features and aspects of the invention may become apparent, from consideration of the following description, In the accompanying drawings: Figure 1 is a block schematic diagram of a known type of analogue to digital converter with associated waveforms; Figure 2 depicts the relationship between output voltage and temperature for a K type thermocouple; Figure 3 depicts the deviation of the thermocouple response from linearity; Figure 4 depicts the deviation of the response characteristic corresponding to Figure 3 when the thermocouple is used as the source Vin for the converter of Figure 1; Figure 5 depicts a corrected response to the converter using known techniques; Figure 6 is a block schematic diagram of an analogue to digital converter modified in accordance with the invention with associated waveforms;; Figures 7 and 8 depict exemplified corrected responses for the converter in accordance with the invention; Figure 9 depicts reading errors for the converter in accordance with the invention; Figure 10 represents the comparison between Figures 4 and 9; Figure 11 is a schematic representation of alternative resistance means for use in the converter of Figure 6; and Figure 12 is a block schematic diagram of another analogue to digital converter using the resistance means of Figure 11.

Figure 1 shows a known dual-slope analogue to digital converter based on an integrated circuit device Intersil ICL 7116. As is known, the converter employs an integrator 10 with an output V1 feeding a comparator 11. Logic control means 12 receives clock pulses fi which are gated by the output from the comparator 11 to provide a count N for display. The input to the integrator 10 is selectively changed by a switch 13 between a voltage sourve Vin and a known reference voltage V ref conveniently provided by the device Intersil ICL 71 16 Additional switches 14, 1 5 serve to selectively connect a reference capacitor Cr between the reference voltage V ref and earth.The switches 13, 14 15 are provided on the device 711 6 and additional means serves selectively to reverse the polarity of the capacitor Cr. The switches 13-1 5 and additional means are controlled by signals from the control means 12. The reference capacitor Cr stores the reference voltage V ref and provides a fixed reference when gated through to the integrator 10. The control means 1 2 causes the converter to operate in sequential phases as depicted by the waveform in Figure 1. More particularly the operation is as follows: Phase 1-Auto zero.

During this phase the errors in the components, such as offset voltages etc are automatically nulled by connecting the integrator input to earth and establishing a feedback loop so that an error voltage is stored by an auto-zero capacitor. The reference capacitor Cr is connected to the reference voltage so that it charges to the reference voltage.

Phase 2-Integrate input signal Vin During this phase, the reference capacitor Cr is held open circuit the signal Vin is connected to the integrator 10 and the control means 12 times a fixed number (N 1 ) of pulses. For a 3 digit converter, and in the present case, 1000 pulses would be typical while for a 49 digit converter 10,000 pulses would be typical. On completion of this period the magnitude of the voltage V1 is directly proportional to the input Vin and the auto-zero capacitor is included in the signal processing circuitry to eliminate the residual errors.

Phase 3-Integrate reference signal V ref.

At the commencement of this phase, the reference voltage V ref as stored by the capacitor C ref is connected to the input to the integrator and the polarity is such that the integrator output Vin falls to zero thereby providing a number of pulses dependent on the value achieved at the end of phase 2.

As depicted in Figure 1, the voltage V1 varies linearly over the phases 2 and 3. The number of pulses N counted over phase 3 is a digital indication of the magnitude of Vin.

The transfer characteristic of this known converter is given by VinxN1 N 1 Vref where: N= count during reference integrate period N1=count during input integrate period V ref=reference voltage Vin=input signal voltage This characteristic is linear.

If the converter is used to provide a digital reading of a voltage Vin which varies with some parameter in a linear manner there is no problem but if some transducer is used to provide the source voltage Vin which has a non-linear response with respect to the parameter then the converter reading itself will not be accurate with respect to that parameter. The error involved depends on the difference in characteristics of the converter and the transducer and to compensate for this difference it is known to impose a non-linear chåracteristic on the response of the converter to closely match the response of the transducer. This can be done empirically and is known as 'characterising' the converter.

By way of example, let it be assumed that the transducer providing the voltage Vin is a K type thermocouple sensing temperature.

Figure 2 depicts the response of this device-(see BS4937 Pt. 4). Over the range of temperature 0 to 1 3720C the response has an average slope of 40 uV/ C but the response is not linear. The deviation of the response from linearity is shown in Figure 3. Using the converter of Figure 1 with the K type thermocouple will produce a reading error with respect to the prevailing temperature as represented in Figure 4. To compensate for the reading error the transducer response can be resolved into a series of linear approximations so that at each change in slope a break point is established and the converter response is adjusted accordingly. Figure 5 depicts a 3 break point approximation of the K type thermocouple response over the range OOC to 1 3720C. This technique is not particularly efficient since it is difficult to identify the break points and a converter adapted for one response cannot be used for another application. For certain responses a large number of break points may need to be established.

In accordance with the present invention the converter is modified as shown in Figure 6. The additional resistors Rr and R2 are capable of characterising the converter over its full operating range.

In contrast to the Figure 1, the voltage V1 varies in a non-linear manner over the phases 2 and 3 as shown and the capacitor Cr provides a dynamically changing reference during the de-integrate period of Phase III.

The transfer characteristics of the modified converter is given by

where: N=count during reference integrate period N 1 =count during input signal integrate period Vref=reference voltage Vin=input voltage fi=count frequency Tr=RrxCr;'ri;=R2xC1 Rr, R2, Cr, Cl :value of the respective components It is not possible to re-express equation 2) so that N is given in terms of Vin. Therefore, if Vin is required to be the independent variable the equation must be solved numerically for N e.g. using the false position method.

Equation 2 is applicable to the mode of operation outlined above in connection with Figure 1 when both terminals of the 'reference' capacitor, Cr are open circuit during the signal integrate period of phase 2. If for any reason, however, terminal Y is left connected to the analogue-common during phase 2 then the equation should be modified since Cr will discharge during this phase. However the characteristics will still take place for suitable parameter values.

For some characteristics Tr or T1 may be very large and therefore one or other of the resistors Rr or R2 respectively may not be inciuded.

For a suitable choice of parameter values, the transfer characteristic described by equation 2 can be made to describe a huge variety of curves and shapes and therefore the converter can be characterised to an equally large number of input transducers. This provides great versatility. The characterisation resulting from this invention is not limited to functions whose derivations are bijective i.e. containing one bend, but extend to functions whose derivatives are surjective only, i.e., containing a number of bends. By characterising the converter in accordance with the invention to approximately image the input transducer characteristic a dramatic reduction in errors and corresponding increase in accuracy can be achieved.

Three of the many characterisations possible by the adapted converter of Figure 6 are shown in Figure 7 and 8. Figure 8 shows the converter characteristic characterised to closely image the type K thermocouple whilst Figure 7 illustrates how the 'bends' in the characteristic can be accentuated or deemphasised around the type K thermocouple response, by altering the parameter values.

For the characterisation of Figure 8 the corresponding reading errors are shown in Figure 9. These are drawn on the same scale as Figure 4 which shows the reading errors for the unmodified converter.

The reduction in the reading errors achieved with the modified converter can be visually appreciated from Figure 10 where the two error graphs-Figure 4 and 9-are redrawn and superimposed.

Figure 7 does not necessarily represent the solution with minimum reading errors. Normally the parameter values would be chosen to trade-off the essential accuracies required against those which are not required or less important.

For the purpose of illustration the converter of Figure 6 has been characterised for the K type thermocouple over the range OOC to 1 3720C. This range is however exemplary and the adapted converter can be used to characterise the negative range OOC to -2700C with equally good results.

Figure 11 depicts a circuit for replacing the resistor Rr of Figure 6. As shown, a device A is incorporated together with a further voltage source V3 and a resistor R'r. The device A provides an overall transfer gain G which may be > 1 or < 1 and adds the voltage V3 (positive or negative) to the voltage Vin. Figure 12 shows the Figure 6 converter further modified to incorporate the circuit of Figure 11 instead of the resistor Rr. As mentioned previously, the device A provides a transfer gain G and by appropriate control of the gain G the same effect as varying the value of the resistor Rr in Figure 6 can be achieved. However, the provision of the source V3 provides a very effective way of adapting the converter to the transducer characteristics as described previously.Thus, for example, if V3 is negative and greater than Vref then the following conditions will prevail: If Vin is low such that Vin+V3 < -V ref the resistor Rr' will decrease the sensitivity of the converter as Vin is de-integrated. Conversely, if Vin is high such that Vin+V3 > -V ref the resistor Rr' will increase the sensitivity of the converter as Vin is de-integrated. In the limiting case where Vin+3=-V ref the resistor Rr' will have no effect on the sensitivity. It thus follows that variation of V3 can alter the sensitivity to match the transducer characteristic. A further modification can be made in Figure 11 to incorporate a switch SW in the line Z from the source V3 as shown in dotted outline. The switch SW can then be controlled by means K detecting the magnitude and/or polarity of the input Vin so as to automatically gate the source V3 to the device A when Vin changes.

Claims

1. An analogue to digital converter employing integrating means for integrating an input voltage derived from a parameter sensed by a transducer with a non-linear response, control means which gates clock pulses providing a digital output and controls switches which connect the integrating means to the input voltage to be measured and to a dynamic reference voltage source provided by a reference capacitor which stores a reference voltage during one phase of operation determined by the control means and the switches and resistance compensating means which constrains the integrating means to provide a response which is substantial linear with respect to the parameter.

2. A converter according to Claim 1, wherein the integrating means is a virtuai-earth operational amplifier with a feedback capacitor and the compensating means at least includes a selected value resistor connected in parallel with the feedback capacitor.

3. A converter according to Claim 1, wherein the compensating means at least includes a selected value resistor connected between a terminal which receives the input voltage and the plate of the reference capacitor which accepts the reference voltage.

4. A converter according to Claim 2, wherein the compensating means further comprises another selected value resistor connected between a terminal which receives the input voltage and the plate of the reference capacitor which accepts the reference voltage.

5. A converter according to Claim 3 or 4, wherein a device is connected in series with the resistor connected to the reference capacitor and said device provides amplification or attenuation.

6. A converter according to Claim 5, wherein said device also combines a further voltage with-the input voltage.

7. A converter according to Claim 6, wherein the further voltage has either positive or negative polarity and said further voltage is selectively connected to said device in dependence on the input voltage.

8. A converter according to any one of Claims 1 to 7, wherein the control means causes the input voltage to be connected to the integrating means for a fixed time interval while the resulting digital output is counted and the dynamic reference voltage stored by the reference capacitor to be thereafter connected to the integrating means to bring the output thereof back to a pre-determined value in a time period dependent on the magnitude of the input voltage, while the digital output is again counted and wherein the compensating means constrains the output of the integrating means to vary in a non linear manner with respect to time.

9. An analogue to digital converter substantially as described with reference to and as illustrated in Figure 6 or Figure 12 of the accompanying drawings.

10. A converter according to Claim 4 or any one of Claims 5 to 8 when appendant to Claim 4, wherein the values of said resistors are calculated in accordance with equation 2 in the accompanying description.

11. The combination of a transducer providing a source of voltage which varies in a non-linear manner with respect to a sensed parameter and a converter according to anyone of the preceding claims.

12. The combination of Claim 11, wherein the transducer is a K type thermocouple.

13. An analogue to digital converter of the type comprising an operational amplifier with capacitive feedback forming an integrating means, switching means for selectively connecting the input of the integrating means to a voltage source derived from a transducer sensing a parameter and to a reference capacitor which stores a reference voltage, control means for controlling the switching means and for gating a sequence of digital pulses having a pre-determined relationship with-the source voltage and capable of producing a corresponding digital read out; wherein additional resistors or the equivalent are connected serially to the reference capacitor and across the capacitive feedback of the operational amplifier and these resistors have values adapted to constrain the integrating means to adopt a transfer response to compensate for non-linearity in the source voltage.