CA1146276A - Analog-to-digital converter apparatus for condition responsive transducer - Google Patents
Analog-to-digital converter apparatus for condition responsive transducerInfo
- Publication number
- CA1146276A CA1146276A CA000331125A CA331125A CA1146276A CA 1146276 A CA1146276 A CA 1146276A CA 000331125 A CA000331125 A CA 000331125A CA 331125 A CA331125 A CA 331125A CA 1146276 A CA1146276 A CA 1146276A
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- CA
- Canada
- Prior art keywords
- signal
- time period
- digital
- analog
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/52—Input signal integrated with linear return to datum
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Radiation Pyrometers (AREA)
- Measuring Fluid Pressure (AREA)
Abstract
Abstract of the Disclosure An analog signal representing the measured output of a condition responsive transducer is supplied to a dual slope integrating analog-to-digital converter also receiving a regulated constant reference signal. Using the integrator in a non-inverting mode, the A/D converter operates in a single conversion cycle by first positively integrating a value of the received analog signal below a maximum negative input voltage for a fixed time period and then negatively integrating a voltage signal corresponding to the differential between the reference voltage signal and the maximum voltage signal for a variable time period to a comparative threshold. During integration, digital counts proportional to the variable integration period are accumulated and emitted for operating a digital device such as a digital display.
Digital linearization of the converter output can optionally be provided by use of a programmed microcomputer reading a programmable-read-only-memory (PROM) to run a variable frequency clock. The clock is regulated to effect a first phase converter time corresponding with an even multiple of the power line frequency.
mb/sb
Digital linearization of the converter output can optionally be provided by use of a programmed microcomputer reading a programmable-read-only-memory (PROM) to run a variable frequency clock. The clock is regulated to effect a first phase converter time corresponding with an even multiple of the power line frequency.
mb/sb
Description
z~
Technical Field The technical field to which the invention pertains relates to the art of dual slope analog-to-digital con-verters for effecting a digital output signal of a measured analog signal being supplied to the converter.
Background of the Invention The dual slope type analog-to-digital dual slope con-verter for effecting a digital output signal from a measured analog input signal is well known as disclosed, for example, in U. S. patents 3,061,939; 3,316,546; 3,458,803, 3,660,834 and 3t566,397. Briefly, the method of conversion involves integrating a current directly related to an unknown voltage for a fixed period of time, followed by the integration of a standard current related to a reference voltage of opposite polarity until the integrator output returns to zero. The total time period required to null the integrator is directly proportional to the ratio of the measured current to the standard current, and, therefore, to the measured voltage.
The integrator, therefore, is a circuit producing a linearly changing output with time (usually a ramp) when the input is some constant voltage and the rate of integrator output voltage increase is directly proportional to the magnitude of input voltage. When input voltage is zero, output voltage is not subject to change but remains zero at whatever output value was achieved at the beginning of the time period.
Standard operation for such prior art converters has included integration of the unknown in the same direction of polarity as the input signal, e. g. positive~to-positive which is then switched to a reference signal of opposite `` 30 polarity that is integrated to zero. This is then detected by a comparator of the integrated signals and for large analog inputs prolonged time periods are required -to effect the zero integration. The digital counts are then accumulated in a register proportional to the time factor associated with the unknown integration.
While this basic arrangement has functioned well with a high order of accuracy, it requires reference switching and polarity detection which becomes difficult at very low inputs leading to switching uncertainties. Also, bias currents associated with these prior devices have added and subtracted from the slopes in each of its changed directions.
For overcoming these deficiencies, it has been necessary to utilize precision low offset amplifiers. Despite recognition of the foregoing, means for effecting their elimination has not heretofore been known.
Summary of the Invention This invention relates to analog-to-digital conversion apparatus for effecting a digital output signal correlated to an analog signal being emitted from a condition responsive ~0 transducer. More specifically, the invention relates to an AtD converter of the dual slope type able to eliminate the reference switching and bias current problems characteristic of such prior art converters whereby to enhance the overall accuracy and reliability of such systems. Optionally, a further feature also affords enhanced linearization of the output signal.
Specifically, the invention relates to a dual slope analog-to-digital converter for emitting a digital output m~ ~ 2 -Z7~
signal corresponding to an analog signal being received, including single cycle conversion means operative to convert the received analog signal to a digital outpu-t signal in a single up-down integration cycle and comprising first input means for receiving an analog voltage signal to be converted, second input means for receiving a reference voltage signal, means for deriving a predetermined maxO voltage signal from the voltage signal of the second input means, means establishing a datum level voltage, integrator means operative seriatim to integrate a first signal corresponding to the differential between the derived max. voltage signal and the received analog signal for a prede-termined time period and on expiration of the predetermined time period to integrate a second signal corresponding to the differential between the reference voltage signal and the max. voltage signal, comparator means adapted to receive the integrated signals for effectively varying the integration time period of the second signal until a predetermined threshold level is achieved between the integrated second signal output of the integrator means and the datum level voltage and signal emitting means for emitting a digital output signal derived from an accumulative digital count correlated to the time span of the variable time period.
Thus, the invention always integrates the unknown analog input signal in a direction polar opposite to a reference signal enabling one of the two prior used reference signals to be eliminated. At the same time there is afforded the ability to both measure and verify polarity of the input .~
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~ .
signal withou-t regard to the signal level. By using the integrator in a non-inverting mode, the A/D converter inte-grates positively all the analog signal values below a maximum negative input voltage while accumulating digital counts proportional to the differences therebetween. A digital display or other appropriate digital device is then operated by the count signals received from the converter. Optionally, digital linearization of the count signals can be provided for mg/-~J~- - 2b -correcting any encountered deviation from ideal linearity.
This is achieved by a programmed microcomputer reading a PROM to run a variable frequency clock via the PROM pro-gramming. The clock frequency is regulated to efect a first phase converter time that corresponds with an even multiple of the power line frequency. Accumulator counts will then vary directly with clock frequency.
It is therefore an object of the invention to provide novel modifications to an analog-to-digital converter of the dual slope type for effecting a digital output signal correlated to a transducer provided analog signal.
It is a further object of the invention to effect the previous object with modifications that effectively elim-inate the reference switching and bias current problems characteristic of similar purpose prior art A/D converters.
Brief Description of the Drawings Fig. 1 is a block diagram of a system apparatus embody-ing the invention;
Fig. 2 is an electronic schematic of the modified dual slope A/D converter hereof;
Fig. 3 is a timing diagram for the dual slope converter of Fig. 2 at zero and non-zero signal levels; and Fig. 4 is an optional variation for the dual slope con-verter of Fig. 2 for affording digital linearization.
Referring first to Fig. 1, there is disclosed a trans-ducer 10 adapted to continuously emit an analog signal Va correlated to the measured value of a condition being measured by the transducer. Transducer 10 can typically be any suitable type measuring instrument from which an analog output can be obtained and in a preferred use may constitute a pressure or temperature transducer as dis-closed, for example, in U. S. patents 3,742,233 or 4,109,147. Analog signal Va from the transducer, along with a reference signal Vr of a known regulated voltage ` 35 as will be explained are both supplied to A/D converter 12 ~` in accordance herewith to in turn emit a count signal Vd ` for any of a variety of applications such as for operating a digital display 14.
Re~e~u~a now to Fig. 2, the modified A/D dual slope ~rr~)ng .
., , ~ .
converter 12 hereof is comprised of a summing amplifier 16, an integrator 18, a comparator and auto-zero amplifier 20, a sample/hold amplifier 22 and a logic and accumulator module 24 which for the embodiment being described is of a commercially available type similar to Na~ional Semi-conductor ~5330 A/D Building Block operative as will be explained below. Analog signal Va, being supplied from transducer 10 in correlation to its measured parameter, is of negative polarity for connection directly through switch SW-l to summing amplifier 16, while reference volt-age Vr, being supplied from a regulated voltage source, is of negative polarity for connection through switch SW-2 to comparator and auto-zero amplifier 20. The output of amplifier 16 is provided through switch SW-3 to the positive terminal of integrator 18 while a Vmax voltage is derived from Vr through dividers Rl and R2 for feeding the negative terminal of integrator 18. By way of example, if maximum positive voltage at Va = 1.9999 volts, Vmax would arbitrarily be set at 2.2000 volts and at Va = zero measurement would be based on 2.2000 volts. Logic and accumulator module 24 provides the logic for sequencing the aforementioned switches.
With reference also to Eig. 3, the complete A/D con-version cycle of transducer signal Va is shown in which Va = 0 volts is the solid slope and Va ~ 0 volts for a measured value not equal to zero has a dashed slope. The cycle from left to right (Fig. 3) consists of three phases being auto-zero phase III, the integrator reference phase I for a predetermined fixed time period Tr and the inte-grated unknown phase II for a variable time period Tx.
During phase III, comparator and auto-zero amplifier 20 functions as a high gain zeroing amplifier that with switch SW-4 closed, drives sample/hold amplifier 22, capacitor C-1 and inverting summing amplifier 16 through switch SW-3 to restore the integrator capacitor C-2 voltage to zero volts.
Switches SW-1, SW-2 and SW-5 during this phase are all in grounded position. Also, because of the characteristics of amplifier 22, all amplifier voltage offsets are stored on capacitor C-l where they remain through the integration
Technical Field The technical field to which the invention pertains relates to the art of dual slope analog-to-digital con-verters for effecting a digital output signal of a measured analog signal being supplied to the converter.
Background of the Invention The dual slope type analog-to-digital dual slope con-verter for effecting a digital output signal from a measured analog input signal is well known as disclosed, for example, in U. S. patents 3,061,939; 3,316,546; 3,458,803, 3,660,834 and 3t566,397. Briefly, the method of conversion involves integrating a current directly related to an unknown voltage for a fixed period of time, followed by the integration of a standard current related to a reference voltage of opposite polarity until the integrator output returns to zero. The total time period required to null the integrator is directly proportional to the ratio of the measured current to the standard current, and, therefore, to the measured voltage.
The integrator, therefore, is a circuit producing a linearly changing output with time (usually a ramp) when the input is some constant voltage and the rate of integrator output voltage increase is directly proportional to the magnitude of input voltage. When input voltage is zero, output voltage is not subject to change but remains zero at whatever output value was achieved at the beginning of the time period.
Standard operation for such prior art converters has included integration of the unknown in the same direction of polarity as the input signal, e. g. positive~to-positive which is then switched to a reference signal of opposite `` 30 polarity that is integrated to zero. This is then detected by a comparator of the integrated signals and for large analog inputs prolonged time periods are required -to effect the zero integration. The digital counts are then accumulated in a register proportional to the time factor associated with the unknown integration.
While this basic arrangement has functioned well with a high order of accuracy, it requires reference switching and polarity detection which becomes difficult at very low inputs leading to switching uncertainties. Also, bias currents associated with these prior devices have added and subtracted from the slopes in each of its changed directions.
For overcoming these deficiencies, it has been necessary to utilize precision low offset amplifiers. Despite recognition of the foregoing, means for effecting their elimination has not heretofore been known.
Summary of the Invention This invention relates to analog-to-digital conversion apparatus for effecting a digital output signal correlated to an analog signal being emitted from a condition responsive ~0 transducer. More specifically, the invention relates to an AtD converter of the dual slope type able to eliminate the reference switching and bias current problems characteristic of such prior art converters whereby to enhance the overall accuracy and reliability of such systems. Optionally, a further feature also affords enhanced linearization of the output signal.
Specifically, the invention relates to a dual slope analog-to-digital converter for emitting a digital output m~ ~ 2 -Z7~
signal corresponding to an analog signal being received, including single cycle conversion means operative to convert the received analog signal to a digital outpu-t signal in a single up-down integration cycle and comprising first input means for receiving an analog voltage signal to be converted, second input means for receiving a reference voltage signal, means for deriving a predetermined maxO voltage signal from the voltage signal of the second input means, means establishing a datum level voltage, integrator means operative seriatim to integrate a first signal corresponding to the differential between the derived max. voltage signal and the received analog signal for a prede-termined time period and on expiration of the predetermined time period to integrate a second signal corresponding to the differential between the reference voltage signal and the max. voltage signal, comparator means adapted to receive the integrated signals for effectively varying the integration time period of the second signal until a predetermined threshold level is achieved between the integrated second signal output of the integrator means and the datum level voltage and signal emitting means for emitting a digital output signal derived from an accumulative digital count correlated to the time span of the variable time period.
Thus, the invention always integrates the unknown analog input signal in a direction polar opposite to a reference signal enabling one of the two prior used reference signals to be eliminated. At the same time there is afforded the ability to both measure and verify polarity of the input .~
mg/~ 2a -.
~ .
signal withou-t regard to the signal level. By using the integrator in a non-inverting mode, the A/D converter inte-grates positively all the analog signal values below a maximum negative input voltage while accumulating digital counts proportional to the differences therebetween. A digital display or other appropriate digital device is then operated by the count signals received from the converter. Optionally, digital linearization of the count signals can be provided for mg/-~J~- - 2b -correcting any encountered deviation from ideal linearity.
This is achieved by a programmed microcomputer reading a PROM to run a variable frequency clock via the PROM pro-gramming. The clock frequency is regulated to efect a first phase converter time that corresponds with an even multiple of the power line frequency. Accumulator counts will then vary directly with clock frequency.
It is therefore an object of the invention to provide novel modifications to an analog-to-digital converter of the dual slope type for effecting a digital output signal correlated to a transducer provided analog signal.
It is a further object of the invention to effect the previous object with modifications that effectively elim-inate the reference switching and bias current problems characteristic of similar purpose prior art A/D converters.
Brief Description of the Drawings Fig. 1 is a block diagram of a system apparatus embody-ing the invention;
Fig. 2 is an electronic schematic of the modified dual slope A/D converter hereof;
Fig. 3 is a timing diagram for the dual slope converter of Fig. 2 at zero and non-zero signal levels; and Fig. 4 is an optional variation for the dual slope con-verter of Fig. 2 for affording digital linearization.
Referring first to Fig. 1, there is disclosed a trans-ducer 10 adapted to continuously emit an analog signal Va correlated to the measured value of a condition being measured by the transducer. Transducer 10 can typically be any suitable type measuring instrument from which an analog output can be obtained and in a preferred use may constitute a pressure or temperature transducer as dis-closed, for example, in U. S. patents 3,742,233 or 4,109,147. Analog signal Va from the transducer, along with a reference signal Vr of a known regulated voltage ` 35 as will be explained are both supplied to A/D converter 12 ~` in accordance herewith to in turn emit a count signal Vd ` for any of a variety of applications such as for operating a digital display 14.
Re~e~u~a now to Fig. 2, the modified A/D dual slope ~rr~)ng .
., , ~ .
converter 12 hereof is comprised of a summing amplifier 16, an integrator 18, a comparator and auto-zero amplifier 20, a sample/hold amplifier 22 and a logic and accumulator module 24 which for the embodiment being described is of a commercially available type similar to Na~ional Semi-conductor ~5330 A/D Building Block operative as will be explained below. Analog signal Va, being supplied from transducer 10 in correlation to its measured parameter, is of negative polarity for connection directly through switch SW-l to summing amplifier 16, while reference volt-age Vr, being supplied from a regulated voltage source, is of negative polarity for connection through switch SW-2 to comparator and auto-zero amplifier 20. The output of amplifier 16 is provided through switch SW-3 to the positive terminal of integrator 18 while a Vmax voltage is derived from Vr through dividers Rl and R2 for feeding the negative terminal of integrator 18. By way of example, if maximum positive voltage at Va = 1.9999 volts, Vmax would arbitrarily be set at 2.2000 volts and at Va = zero measurement would be based on 2.2000 volts. Logic and accumulator module 24 provides the logic for sequencing the aforementioned switches.
With reference also to Eig. 3, the complete A/D con-version cycle of transducer signal Va is shown in which Va = 0 volts is the solid slope and Va ~ 0 volts for a measured value not equal to zero has a dashed slope. The cycle from left to right (Fig. 3) consists of three phases being auto-zero phase III, the integrator reference phase I for a predetermined fixed time period Tr and the inte-grated unknown phase II for a variable time period Tx.
During phase III, comparator and auto-zero amplifier 20 functions as a high gain zeroing amplifier that with switch SW-4 closed, drives sample/hold amplifier 22, capacitor C-1 and inverting summing amplifier 16 through switch SW-3 to restore the integrator capacitor C-2 voltage to zero volts.
Switches SW-1, SW-2 and SW-5 during this phase are all in grounded position. Also, because of the characteristics of amplifier 22, all amplifier voltage offsets are stored on capacitor C-l where they remain through the integration
2'~;
cycle serving to eliminate even large offset voltages.
During phase I, in response to a received power line sync signal, switches SW-4 and SW-5 are opened. Refer-ence voltage Vr is applied through switch SW-2 to amplifier 20 for simultaneously establishing Vmax via divider Rl and R2. Vmax is chosen based on the full scale counts desired. At the same time, Va is connected to the input integrator 18 via summing amplifier 16 and switch SW-3.
The output of integrator 18 then slews to Va for integra-tion to begin for a reference period Tr during which time integration occurs for a signal value based on the differ-ential between (Vmax ~ Va). Time Tr is preferably selected to be of some even multiple of the local power line fre-quency for increasing the normal mode noise rejection of the converter.
On completion of phase I, phase II is initiated dur-ing which reference voltage Vr is applied to integrator 18 for the unknown period Tx until the threshold of compara-tor 20 is crossed in its comparison between the signal levels of Vr and the integrator output. At such time, coincident with the comparator output, the digital counts which accumulated during integration period Tx are transferred from the counter to the latches, the parallel output signal of which Vd is applied to display unit 14 or transmitted elsewhere as desired. The latter can be understood by the following example in which:
o Cf ~here CO = counts overflow f = clock frequency (HZ) assuming third harmonic of 60HZ = .050 sec.
and CO = 18000 then Cf = 36000 HZ
Where Va equal zero and Vmax is measured, a complete conversion will occur on the basis of:
z~
Tc = Tr -t Tx (Fig. 3) 360000 ~ 360000 = 0.111111 sec.
with + 0000 displayed.
For any positive Va less than V a the code converter 9's complements the counter to display the measured value.
In this manner, display 14 yields a linear conversion for Va less than V
max For effecting digital linearization usable with A/D
converter 12 or with any dual slope standard system, reference is made to Fig. 4 in which there is shown a schematic circuit therefor including a microcomputer 26, the PROM 28 and a variable frequency clock source 30 connected to logic and accumulator module 24. During phase I (Fig. 3), microcomputer 26 reads PROM 28 for receipt of programmed information to drive clock 30 at a frequency such that Tr is an even multiple of the power line frequency. Each of microcomputer 26, PROM 28 and clock 30 are commercially available from various manufacturers. Microcomputer 26 can, for example, comprise a single chip microcomputer manufactured by Fairchild Camera and Instrument or Mostek Corp. under the designation `-F3870'' while PROM 28 can be obtained from either Signetics under their commercial designation 'DM74S188 or from Texas Instruments under their commercial designation -SN74188-'. Oscillator 30 is available as a 74LSO4 gate with crystal feedback while the counters are 74LS193 types, both manufactured by various integrated circuit manufacturers such as National ~' Semiconductor.
.
~ mb/~ - 6 -.
. . ~ .
~6~6 Phase II is sensed by the microcomputer on the convert line Co and based on information received from PROM 28 drives the frequency of clock 30 at various rates per unit time as programmed into PROM 28.
In this manner, clocking frequencies that are different between phases II and I do not affect the conversion time which instead remains cons-tant for a given input voltage Va. Integrator 18 functions in the same manner as described above while the counts accumulated during time period Tx will vary more directly dependent on the frequency of clock 30. Should Va be a non-linear response of some linear function being measured, the final accumulated counts are therefor adjusted in that manner to yield a linear digital representation of the measurement.
If, for example, different clocking frequencies are utilized during phase II than phase I, the conversion time nevertheless remains the same for a given input voltage Va since integrator 18 makes the same excursion. The counts accumulated during Tx will be more or less depending on the frequency of clock 30 such that the accumulated counts over the course of Tx can be varied in direct relation to the ~, value of Va. Using the previous example and va~
-~ mb/ ~ - 6a -k~
the clocking frequency a number of times (n) then when n = 5 Tn = Tx = .0122222 and Nt = Tn (F2) + Tn (F3) + Tn (F4) + Tn (Fs) + Tn (F6) where Fl = clock frequency during Tr = 360 KHZ
2 " Tx = 350
cycle serving to eliminate even large offset voltages.
During phase I, in response to a received power line sync signal, switches SW-4 and SW-5 are opened. Refer-ence voltage Vr is applied through switch SW-2 to amplifier 20 for simultaneously establishing Vmax via divider Rl and R2. Vmax is chosen based on the full scale counts desired. At the same time, Va is connected to the input integrator 18 via summing amplifier 16 and switch SW-3.
The output of integrator 18 then slews to Va for integra-tion to begin for a reference period Tr during which time integration occurs for a signal value based on the differ-ential between (Vmax ~ Va). Time Tr is preferably selected to be of some even multiple of the local power line fre-quency for increasing the normal mode noise rejection of the converter.
On completion of phase I, phase II is initiated dur-ing which reference voltage Vr is applied to integrator 18 for the unknown period Tx until the threshold of compara-tor 20 is crossed in its comparison between the signal levels of Vr and the integrator output. At such time, coincident with the comparator output, the digital counts which accumulated during integration period Tx are transferred from the counter to the latches, the parallel output signal of which Vd is applied to display unit 14 or transmitted elsewhere as desired. The latter can be understood by the following example in which:
o Cf ~here CO = counts overflow f = clock frequency (HZ) assuming third harmonic of 60HZ = .050 sec.
and CO = 18000 then Cf = 36000 HZ
Where Va equal zero and Vmax is measured, a complete conversion will occur on the basis of:
z~
Tc = Tr -t Tx (Fig. 3) 360000 ~ 360000 = 0.111111 sec.
with + 0000 displayed.
For any positive Va less than V a the code converter 9's complements the counter to display the measured value.
In this manner, display 14 yields a linear conversion for Va less than V
max For effecting digital linearization usable with A/D
converter 12 or with any dual slope standard system, reference is made to Fig. 4 in which there is shown a schematic circuit therefor including a microcomputer 26, the PROM 28 and a variable frequency clock source 30 connected to logic and accumulator module 24. During phase I (Fig. 3), microcomputer 26 reads PROM 28 for receipt of programmed information to drive clock 30 at a frequency such that Tr is an even multiple of the power line frequency. Each of microcomputer 26, PROM 28 and clock 30 are commercially available from various manufacturers. Microcomputer 26 can, for example, comprise a single chip microcomputer manufactured by Fairchild Camera and Instrument or Mostek Corp. under the designation `-F3870'' while PROM 28 can be obtained from either Signetics under their commercial designation 'DM74S188 or from Texas Instruments under their commercial designation -SN74188-'. Oscillator 30 is available as a 74LSO4 gate with crystal feedback while the counters are 74LS193 types, both manufactured by various integrated circuit manufacturers such as National ~' Semiconductor.
.
~ mb/~ - 6 -.
. . ~ .
~6~6 Phase II is sensed by the microcomputer on the convert line Co and based on information received from PROM 28 drives the frequency of clock 30 at various rates per unit time as programmed into PROM 28.
In this manner, clocking frequencies that are different between phases II and I do not affect the conversion time which instead remains cons-tant for a given input voltage Va. Integrator 18 functions in the same manner as described above while the counts accumulated during time period Tx will vary more directly dependent on the frequency of clock 30. Should Va be a non-linear response of some linear function being measured, the final accumulated counts are therefor adjusted in that manner to yield a linear digital representation of the measurement.
If, for example, different clocking frequencies are utilized during phase II than phase I, the conversion time nevertheless remains the same for a given input voltage Va since integrator 18 makes the same excursion. The counts accumulated during Tx will be more or less depending on the frequency of clock 30 such that the accumulated counts over the course of Tx can be varied in direct relation to the ~, value of Va. Using the previous example and va~
-~ mb/ ~ - 6a -k~
the clocking frequency a number of times (n) then when n = 5 Tn = Tx = .0122222 and Nt = Tn (F2) + Tn (F3) + Tn (F4) + Tn (Fs) + Tn (F6) where Fl = clock frequency during Tr = 360 KHZ
2 " Tx = 350
3 " " = 340
4 ' " = 300 " = 360 10 F6 = " " = 450 Nt = 21997 and if the dual s]ope converter hereof reaches crossover Tx = .0366666 seconds, three corrections have occurred and the display will read:
22000 - Tn (Fl + F2 + F3) = 9902 counts In the same example with a constant clocking frequency Tx = .0611111 Tn = .0122222 giving an Nt = 21999 and Linear Display =
22000 - 13200 = 8800 counts Comparison of the above examples shows that in both cases the total number was essentially the same but the non-linear accumulation resulted in a 1102 count increase for a given Va = Tx.
By the above description there is disclosed a novel modification of an analog-to-digital dual slope type con-verter able to give a linear digital representation of a non-linear analog signal representing the measured output of a condition responsive element. By use of relatively inexpensive non-critical components, the precision elements required for eliminating the inherent problems of standard ` 30 dual slope systems are thereby avoided. When employing linearization in accordance herewith, greater flexibility is afforded as compared to analog summing techniques previously utilized. Moreover, the linearization attains ~` the precision of a digital correction that is highly repeatable and inherently temperature stable with the ability to tailor the response from one instrument to the other. Whereas the linearization has been described in combination with the modified dual slope converter hereof, ~` .
.
it is not intended to be so limited since it could be readily utilized with such standard unmodified dual slope converters of the prior art.
Since many changes could be made in the above con-struction and many apparently widely different embodiments of this invention could be made without departing from the scope thereof, it is intended that all matter con-tained in the drawings and specification shall be interpreted as illustrative and not in a limiting sense.
.
. ~
22000 - Tn (Fl + F2 + F3) = 9902 counts In the same example with a constant clocking frequency Tx = .0611111 Tn = .0122222 giving an Nt = 21999 and Linear Display =
22000 - 13200 = 8800 counts Comparison of the above examples shows that in both cases the total number was essentially the same but the non-linear accumulation resulted in a 1102 count increase for a given Va = Tx.
By the above description there is disclosed a novel modification of an analog-to-digital dual slope type con-verter able to give a linear digital representation of a non-linear analog signal representing the measured output of a condition responsive element. By use of relatively inexpensive non-critical components, the precision elements required for eliminating the inherent problems of standard ` 30 dual slope systems are thereby avoided. When employing linearization in accordance herewith, greater flexibility is afforded as compared to analog summing techniques previously utilized. Moreover, the linearization attains ~` the precision of a digital correction that is highly repeatable and inherently temperature stable with the ability to tailor the response from one instrument to the other. Whereas the linearization has been described in combination with the modified dual slope converter hereof, ~` .
.
it is not intended to be so limited since it could be readily utilized with such standard unmodified dual slope converters of the prior art.
Since many changes could be made in the above con-struction and many apparently widely different embodiments of this invention could be made without departing from the scope thereof, it is intended that all matter con-tained in the drawings and specification shall be interpreted as illustrative and not in a limiting sense.
.
. ~
Claims (18)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a dual slope analog-to-digital converter for emitting a digital output signal corresponding to an analog signal being received, single cycle conversion means operative to convert the received analog signal to a digital output signal in a single up-down integration cycle and comprising first input means for receiving an analog voltage signal to be converted, second input means for receiving a reference voltage signal, means for deriving a predetermined max. voltage signal from the voltage signal of said second input means, means establishing a datum level voltage, integrator means operative seriatim to integrate a first signal corresponding to the differential between the derived max. voltage signal and the received analog signal for a predetermined time period and on expiration of said predetermined time period to integrate a second signal corresponding to the differential between said reference voltage signal and said max. voltage signal, comparator means adapted to receive said integrated signals for effectively varying the integration time period of said second signal until a predetermined threshold level is achieved between the integrated second signal output of said integrator means and said datum level voltage and signal emitting means for emitting a digital output signal derived from an accumulative digital count correlated to the time span of said variable time period.
2. In a dual slope converter according to claim 1 in which said integrating means is operative in a non-inverting mode.
3. In a dual slope converter according to claim 2 in which said comparator effectively varies said variable time period in proportion to the level of analog signal received at said first input means.
4. In a dual slope converter according to claim 3 in which said integrator means is operative to integrate said first signal value in a direction polar opposite to the polarity of the received reference signal.
5. In a dual slope converter according to claim 4 in which the predetermined time period of said integrator means comprises an even multiple of the power line frequency with which the converter is to be utilized.
6. In a dual slope converter according to claim 4 including linearization means operative to correct for non-linearity in the digital count from which the output signal of said signal emitting means is derived.
7. In a dual slope converter according to claim 6 in which said linearization means includes a variable frequency clock and means operative to drive said clock during said predetermined time period of said integrator means at a frequency comprising an even multiple of the power line frequency at which converter is to be used and to drive said clock during said variable time period at controlled enjoys in frequency per unit of time in accordance with deviation from linearity of the analog signal being received at said first input.
mb/sb
mb/sb
8. In a dual slope converter according to claim 7 in which said linearization means includes a programmable-read-only-memory (PROM) programmed to change the clock frequency at varying rates per unit of time during said variable time period.
9. A digital output system for continuously emitting a digital signal corresponding to values of a measured condition, the combination comprising a condition responsive transducer adapted to be exposed to the condition to be measured and operative to emit an analog voltage signal continuously correlated to the measured value thereof, a dual slope analog-to-digital converter, said converter having means for effecting single cycle conversion operative to convert the received analog signal to a digital output signal in a single up-down integration cycle and including first input means for receiving the analog voltage signal emitted by said transducer, second input means for receiving a reference voltage signal, means for deriving a predetermined max.
voltage signal from the voltage signal of said second input means, means establishing a datum level voltage, integrator means operative seriatim to integrate a first signal corresponding to the differential between the derived max. voltage signal and the received analog signal for a predetermined time period and on expiration of said predetermined time period to integrate a second signal corresponding to the differential between said reference voltage signal and said max. voltage signal, comparator mb/sb means adapted to receive said integrated signals for effectively varying the integration time period of said second signal until a predetermined threshold level is achieved between the integrated second signal output of said integrator means and said datum level voltage and signal emitting means for emitting a digital output signal derived from an accumulative digital count correlated to the time span of said variable time period, and utilization means for receiving the emitted signal of said signal emitting means.
voltage signal from the voltage signal of said second input means, means establishing a datum level voltage, integrator means operative seriatim to integrate a first signal corresponding to the differential between the derived max. voltage signal and the received analog signal for a predetermined time period and on expiration of said predetermined time period to integrate a second signal corresponding to the differential between said reference voltage signal and said max. voltage signal, comparator mb/sb means adapted to receive said integrated signals for effectively varying the integration time period of said second signal until a predetermined threshold level is achieved between the integrated second signal output of said integrator means and said datum level voltage and signal emitting means for emitting a digital output signal derived from an accumulative digital count correlated to the time span of said variable time period, and utilization means for receiving the emitted signal of said signal emitting means.
10. A system according to claim 9 in which said converter integrating means is operative in a non-inverting mode.
11. A system according to claim 10 in which said comparator effectively varies said variable time period in proportion to the level of the received transducer signal.
12. A system according to claim 11 in which said converter integrator means is operative to integrate said first signal value in a direction polar opposite to the polarity of the received reference signal.
13. A system according to claim 12 in which the predetermined time period of said converter integrator means comprises an even multiple of the power line frequency with which the system is to be utilized.
14. A system according to claim 12 including linearization means operative to correct for non-linearity in the digital count from which the output signal of said signal emitting means is derived.
mb/sb 12
mb/sb 12
15. A system according to claim 12 in which said transducer is temperature sensitive for emitting an analog signal correlated to the temperature of the measured condition.
16. A system according to claim 12 in which said transducer is pressure sensitive for emitting an analog signal correlated to the pressure of the measured condition.
17. A system according to claims 9, 13 or 14 in which said utilization means comprises a digital display device.
18. A system according to claims 14 or 15 in which said utilization means comprises a digital display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000409808A CA1151303A (en) | 1978-09-05 | 1982-08-19 | Linearizing system for dual slope analog-to-digital converter |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US93931578A | 1978-09-05 | 1978-09-05 | |
| US939,315 | 1978-09-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1146276A true CA1146276A (en) | 1983-05-10 |
Family
ID=25472940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000331125A Expired CA1146276A (en) | 1978-09-05 | 1979-07-04 | Analog-to-digital converter apparatus for condition responsive transducer |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPS5537100A (en) |
| BE (1) | BE878605A (en) |
| CA (1) | CA1146276A (en) |
| CH (1) | CH633397A5 (en) |
| DE (1) | DE2935831A1 (en) |
| FR (1) | FR2435861B1 (en) |
| GB (2) | GB2030392B (en) |
| IN (1) | IN152608B (en) |
| NL (1) | NL7905747A (en) |
| SE (2) | SE437591B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4595906A (en) * | 1982-08-12 | 1986-06-17 | Intersil, Inc. | Scaled analog to digital coverter |
| DE3906754A1 (en) * | 1989-03-03 | 1990-09-13 | Messerschmitt Boelkow Blohm | INTEGRATION ARRANGEMENT |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3061939A (en) * | 1959-02-26 | 1962-11-06 | Toyozawa Yoji | Precise measuring method for an inner diameter of a cylinder |
| US3316546A (en) * | 1963-10-15 | 1967-04-25 | Westinghouse Electric Corp | Analog to digital converter system |
| US3458803A (en) * | 1966-03-21 | 1969-07-29 | David E Maguire | Apparatus and method for directly measuring capacitance and dissipation factor of capacitors |
| GB1211755A (en) * | 1967-03-20 | 1970-11-11 | Westinghouse Electric Corp | Analog-to-digital conversion system |
| US3566397A (en) * | 1969-01-15 | 1971-02-23 | Ibm | Dual slope analog to digital converter |
| FR2041678A5 (en) * | 1969-05-28 | 1971-01-29 | Schlumberger Cie N | |
| GB1390064A (en) * | 1971-03-03 | 1975-04-09 | Zschimmer G | Methods and apparatus for use in analogue-digital conversion |
| US3742233A (en) * | 1971-08-20 | 1973-06-26 | Dresser Ind | Motion displacement transducer |
| US3747089A (en) * | 1971-11-09 | 1973-07-17 | K Sharples | Analog to digital converter |
| JPS4939547A (en) * | 1972-08-22 | 1974-04-13 | ||
| US3939459A (en) * | 1974-01-09 | 1976-02-17 | Leeds & Northrup Company | Digital signal linearizer |
| US3967270A (en) * | 1974-07-08 | 1976-06-29 | Essex International, Inc. | Analog-to-digital converter |
| JPS5138546A (en) * | 1974-09-28 | 1976-03-31 | Takeda Maiyaa Kk | KURIIRUSUTANDO |
| JPS52444A (en) * | 1975-06-23 | 1977-01-05 | Advantest Corp | Analog-digital converter |
| JPS524765A (en) * | 1975-06-30 | 1977-01-14 | Hewlett Packard Yokogawa | Dual slope analoggtoodigital converter |
| JPS52131447A (en) * | 1976-04-28 | 1977-11-04 | Toshiba Corp | Bipolar a/d converter |
| US4109147A (en) * | 1976-05-10 | 1978-08-22 | Dresser Industries, Inc. | Optical position sensor |
| JPS5245250A (en) * | 1976-10-07 | 1977-04-09 | Yokogawa Hokushin Electric Corp | Analog to digital convertor |
| DE2747338A1 (en) * | 1977-10-21 | 1979-04-26 | Hartmann & Braun Ag | Two-ramp A=D converter - has shift register and logic circuits to control slope |
-
1979
- 1979-07-04 CA CA000331125A patent/CA1146276A/en not_active Expired
- 1979-07-09 IN IN498/DEL/79A patent/IN152608B/en unknown
- 1979-07-25 NL NL7905747A patent/NL7905747A/en not_active Application Discontinuation
- 1979-07-27 GB GB7926181A patent/GB2030392B/en not_active Expired
- 1979-07-27 GB GB08203839A patent/GB2103442B/en not_active Expired
- 1979-08-29 SE SE7907192A patent/SE437591B/en not_active IP Right Cessation
- 1979-09-03 FR FR7921995A patent/FR2435861B1/en not_active Expired
- 1979-09-03 DE DE19792935831 patent/DE2935831A1/en active Granted
- 1979-09-04 CH CH798179A patent/CH633397A5/en not_active IP Right Cessation
- 1979-09-05 JP JP11402979A patent/JPS5537100A/en active Pending
- 1979-09-05 BE BE0/197017A patent/BE878605A/en not_active IP Right Cessation
-
1984
- 1984-11-27 SE SE8405983A patent/SE8405983L/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| DE2935831A1 (en) | 1980-03-13 |
| FR2435861A1 (en) | 1980-04-04 |
| JPS5537100A (en) | 1980-03-14 |
| GB2030392B (en) | 1983-03-30 |
| GB2103442B (en) | 1983-08-03 |
| SE8405983D0 (en) | 1984-11-27 |
| NL7905747A (en) | 1980-03-07 |
| SE7907192L (en) | 1980-03-06 |
| IN152608B (en) | 1984-02-18 |
| SE437591B (en) | 1985-03-04 |
| SE8405983L (en) | 1984-11-27 |
| BE878605A (en) | 1979-12-31 |
| GB2030392A (en) | 1980-04-02 |
| CH633397A5 (en) | 1982-11-30 |
| FR2435861B1 (en) | 1986-05-09 |
| DE2935831C2 (en) | 1991-11-14 |
| GB2103442A (en) | 1983-02-16 |
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| Date | Code | Title | Description |
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| MKEX | Expiry |