NL7905747A - ANALOG / DIGITAL CONVERTER FOR CONDITIONAL TRANSDUCTOR. - Google Patents

Description

i; * S * DRESSER INDUSTRIES ^ INC., Dallas, Texas, USA St. America

Analog / digital converter for state-of-the-art transducers.

The field to which the invention pertains relates to the technique of dual-slope analog-to-digital converters for supplying a digital output of a measured analog signal to the converter.

The dual-slope analog-to-digital converter for obtaining a digital output from a measured analog input is known from, for example, U.S. Pat. Nos. 3,061,939, 3,316,546, 3,458,803, 3,660,834, and 3,566,397 . Briefly, the method of conversion includes integrating a current in direct relation to an unknown voltage for a fixed period of time, followed by integrating a standard current in relation to a reference voltage of opposite polarity until the integrator output returns to zero. The total time period required to zero the integrator is directly proportional to the ratio of the measured current to the standard current and thus to the measured voltage. The integrator is therefore a circuit, which provides a linearly changing output with time (usually a slope) when the input is a constant voltage and the degree of integrator output voltage increase is directly proportional to the value of the input voltage. When the input voltage is zero, the output voltage is not subject to change, but remains zero at whatever output value was obtained at the beginning of the time period.

Standard operation of such known converters has included integration of the unknown in the same polarity direction as the input signal, for example positive to positive, which is then switched to a reference signal of opposite polarity, which is integrated to zero. This is then detected by a comparator of the integrated signals, and for large analog inputs 7905747 2 $ + 1 t, longer time periods are required to perform the zero integration. The digital counts are then collected in a register proportional to the time factor associated with the unknown integration.

While this basic device has worked well with a high order of accuracy, it requires reference circuitry and polarity detection, which becomes difficult at very low inputs, leading to switching uncertainties. Also, bias currents associated with these known devices have been added and subtracted from the slopes in each of its changed directions. To overcome these difficulties, it is necessary to use accurate low differential amplifiers. Despite this, organs for obtaining elimination thereof are heretofore unknown.

The invention relates to analog-to-digital converters for obtaining a digital output signal associated with an analog signal transmitted from a state-responsive transducer. In particular, the invention relates to a dual-slope analog / digital converter capable of eliminating the reference switching and bias current problems of such known converters, thereby increasing the overall accuracy and reliability of such systems.

Optionally, a further property also provides improved linearity of the output signal.

The above is obtained according to the invention by always integrating the unknown analog input signal in a polarity direction opposite to a reference signal, whereby it is possible to eliminate one of the two previously used reference signals. At the same time, the power is obtained to both measure and determine the polarity of the input signal without regard to the signal level. Using the integrator in a non-reversal mode, the analog / digital converter positively integrates all analog signal values below a maximum negative input voltage, while accumulating digital counts proportional to the differences between them. A digital display or other suitable digital device is then operated by the count signals received from the converter. Optionally, digital linearity of the count signals can be provided to correct any deviation from the ideal 7905747 * t 3 $ linearity. This is accomplished by a programmed microcomputer, which reads a PROM for running a variable frequency clock through the PROM programming. The clock frequency is controlled to perform a first phase converter time corresponding to an even multiple of the power line frequency. Accumulator counts will then vary directly with the clock frequency.

It is an object of the invention to provide a modified double-slope type analog / digital converter for obtaining a digital output signal in connection with a trans-10 ducer providing an analog signal.

A further object of the invention is to effectively eliminate reference switching and bias current problems with corresponding known analog / digital converters.

The invention will be explained in more detail below with reference to the drawing.

Figure 1 shows a block diagram of a device according to the invention.

Figure 2 shows an electronic circuit of the dual slope analog / digital converter.

Figure 3 shows a time diagram for the double slope converter of Figure 2 at zero and non-zero signal levels.

Figure 4 shows a possible variation of the converter of Figure 2 to obtain digital linearity.

In Figure 1, a transducer 10 is arranged to continuously transmit an analog signal Va related to the measured value of a state measured by the transducer. Typically, transducer 10 may be any suitable type of measuring instrument from which an analog output can be obtained, and in a preferred application it may form a pressure or temperature transducer, for example as in U.S. Pat. Nos. 3,742,233 and 4,109,147. The analog signal Va from the transducer, along with a reference signal Vr of a known controlled voltage, as explained below, is supplied to an analog / digital converter 12, which in turn transmits a count signal Vd for a variety of applications, as for operating a digital display 14.

7905747 4 «'** ϊ, 1 l

According to FIG. 2, the dual slope analog / digital converter 12 consists of a summing amplifier 16, an integrator 18, a comparator and auto-zero amplifier 20, a sample / hold amplifier 22, and a logic and storage module 24, which may be 5 of the type of National Semi-conductor MM5330 A / D Building Block, operating ds is described below. The analog signal Va from the transducer 10 in connection with its measured parameter is of negative polarity for direct connection through a switch SW-1 to summing amplifier 16, while the reference voltage Vr supplied from a controlled voltage source is of negative polarity for connection via a switch SW-2 to comparator and auto-zero amplifier 20. The output of amplifier 16 is supplied via a switch SW-3 to the positive terminal of integrator 18 while a Vmax voltage is derived from Vr via dividers Rj and R2 for feeding the negative terminal of the integrator 18. If, for example, maximum positive voltage at Va = 1,9999 volts, V would be optionally set to ΧΩβΧ 2,2000 volts and at Va = zero the measurement would be based at 2,2000 volts. Logic and collection module 24 provides the logic for the sequence of the above switches.

In connection with Figure 3, the entire analog / digital conversion cycle of the transducer signal Va is indicated, where Va = 0 volts is the solid inclined line and Va Φ 0 volts for a measured value not equal to zero is a dotted inclined line. The left to right cycle in Figure 3 consists of three phases, namely the auto-zero phase III, the integrator reference phase I for a predetermined fixed time period and the integrated unknown phase II for a variable time period Tx. During phase III, the comparator and auto-zero amplifier 20 acts as a high-gain zero-gain amplifier, which closes when the switch SW-4 is closed, driving the sample / holding-30 amplifier 22 and capacitor C1, and reversing amplifier 16 via switch. SW-3 for restoring the integrator capacitor C-2 voltage to zero volts. Switches SW-1, SW-2 and SW-5 are grounded during this phase. Also, because of the properties of the amplifier 22, all the amplifier voltage differences are stored in the capacitor C-1, where they remain during the integration cycle, eliminating even large differential voltages.

7905747 • - * 4 5

During phase I, the switches SW-4 and SW-5 are opened due to a received power line synchronization signal. The reference voltage Vr is applied via switch SW-2 to the amplifier 20 to simultaneously form V via the divider Rt, R_. V is chosen based on the desired full scale counts.

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At the same time, Va is connected to the input of the integrator 18 via summing amplifier 16 and switch SW-3. The output of the integrator 18 then swings to Va for integration to start a reference period Tr, during which time integration occurs for a signal value based on the difference (vmax ”Va). The time Tr is preferably chosen as an even multiple of the local power line frequency to increase the normal noise rejection of the converter.

Upon completion of the phase I, the phase II 15 is initiated, during which the reference voltage Vr is applied to the integrator 18 for an unknown period Tx until the threshold of the comparator 20 is exceeded in its comparison between the signal levels of Vr and the integrator output . At such time, coinciding with the comparator output, the digital counts accumulated during the integration period Tx are transferred from the counter to the latches, the parallel output signal Vj of which is applied to the display unit 14 or elsewhere, such as desirable. This will be clear from the following example:

C

25 Tr »-— where C = overflow counts

O

= clock frequency (Hz) assumed the third harmonic of 60 Hz = 0.050 sec.

and C 3 18,000 so that o 30 C. = 36,000 Hz.

t

When Va equals zero and V is measured, max ° full conversion will occur based on: T = Tr + Tx (Figure 3)

O

"" 18,000, 22,000 35 Tc 360,000 360,000 "0.111111 sec * with + 0000 displayed.

7905747 G- * * 1 1 6

For a positive value of Va less than V χ, the code converter 9's complement operation of the counter for displaying the measured value. In this way, the display 14 provides a linear conversion for Va less than V e max. 5 For performing digital linearity usable at the analog / digital converter 12 or a standard double-heal system, reference is made to Figure 4, where one See schematic circuit, provided with a microcomputer 26, a PROM 28 and a variable frequency clock source 30 connected to a logic 10 and collecting module 24. During phase I (Figure 3), the microcomputer 26 reads the PROM 28 to receive programmed information for driving the clock 30 at a frequency such that Tr is an even multiple of the power line frequency.

The phase II is tested by the microcomputer on the reversing line Co and based on information received from PROM 28 it drives the frequency of the clock 30 at different speeds per time unit as programmed in PROM 28. In this way, clock frequencies, which are different between phases II and I not the turnover time, which instead remains constant for a given input voltage Va. The integrator 18 operates in the same manner as described above, while the counts accumulated during the time period Tx will vary more directly depending on the frequency of the clock 30. If Va is a non-linear response to a linear function being measured, therefore, the final accumulated counts are set in such a way that a linear digital representation of the measurement is obtained.

For example, if different clock frequencies are used during phase II relative to phase I, the turnover time nevertheless remains the same for a given input voltage Va since the integrator 18 performs the same excursion. The counts accumulated during Tx will depend more or less on the frequency of the clock 30, so that the accumulated counts can be varied over the course of Tx in direct relation to the value Va.

35 If you use the previous example and you vary the clock frequency a number of (n) times, then at n = 5: 7905747 7 Τη = ~ = 0.0122222 and 5

Nt = Τη (F2) + Τη (Fg) + Τη (F4) + Τη (F $) + Τη (Eg) where Fj = clock frequency during Tr = 360 kHz F2 = "" Tx = 350 kHz 5 F3 «" "M = 340 kHz F4 = "" "= 300 kHz F5 =" "" = 360 kHz

Fg »" "" = 450 kHz

Nt = 21997 and if the double slope converter reaches 10 intersection, Tx = 0.0366666 sec., Three corrections have occurred and the display will read: 22000 - Tn (Fj + F2 + F) = 9902 counts.

In the same example with a constant clock frequency, it is: 15 Tx - 0.0613111 Tn - 0.0122222 which gives an Nt * 21999 and a linear display = 22,000 - 13,200 * 8800 counts.

Comparison of the above examples shows that in both cases the total number was essentially the same, but the nonlinear collection resulted in a 1102 count increase for a given Va = Tx.

Above, a modification of a dual slope analog-to-digital converter suitable for providing a linear digital display of a non-linear analog signal representing the measured output of a state-responsive element has been indicated. By using relatively inexpensive non-critical components, the precision elements necessary to eliminate the inherent problems of standard double slope systems are avoided. By using the linearity according to the invention, greater flexibility is provided compared to previously used analog summing techniques. In addition, linearity obtains the precision of a digital correction, which is highly reproducible and inherently temperature stable with the ability to form the response from one instrument to another. Although the linearization has been described in combination with the double slope converter herewith, it is not so that the invention is so limited as it can be easily used with standard dual slope converters of the prior art.

It will be clear that changes are possible within the scope of the invention.

7905747

Claims (20)

Dual-slope analog-to-digital converter for outputting a digital output signal corresponding to a received analog signal, characterized in that first input means 5 are provided for receiving a convertible analog voltage signal, second input means for receiving a reference voltage signal from which a predetermined maximum voltage signal is derived, integrator means operating sequentially to integrate a first signal value corresponding to the difference between the derived maximum voltage signal and the received analog signal during a predetermined period of time and afterwards of this predetermined time period to integrate a second signal value corresponding to the sum of the first integrated signal and the reference signal, comparators arranged to receive these integrated signals for effectively varying the integration time period of the two the signal value until a predetermined threshold level is reached between the output of the integrator means and the reference signal and signal emitting means for transmitting a digital output signal derived from a collection digital count related to the time course of the variable time period. Transducer according to claim 1, characterized in that the integrators operate in a non-reversal mode. Device according to claim 2, characterized in that the comparator effectively varies the variable time period in proportion to the level of the analog signal received at the first input means. 4. Device according to claim 3, characterized in that the integrator means act to integrate the first signal value in a polarity direction opposite to the polarity of the received reference signal. Device according to claim 4, characterized in that the predetermined period of time of the integrator members consists of an even multiple of the supply line frequency using the converter 35. The device according to claim 4, characterized by 7905747 -. * * »V that linearity means operate to correct the non-linearity in the digital count from which the output signal of the signal emitting means is derived. Device according to claim 6, characterized in that the linearity members consist of a clock of variable frequency and means for driving the clock during the predetermined period of time of the integrator members at a frequency consisting of an even multiple of the power line frequency, the converter operates and drives the clock during the variable time period at controlled frequency changes per unit time in accordance with deviation from the linearity at the analog signal received at the first input. Device according to claim 7, characterized in that the linearity members consist of a programmable read-only memory (PROM) programmed to change the clock frequency at varying rates per unit time during the variable period of time. 9. Digital output system for continuously transmitting a digital signal corresponding to values of a measured state, characterized in that a state-responsive transducer is arranged to be exposed to the measured state and serving transmitting an analog voltage signal continuously in connection with the measured value thereof, an analog / digital converter with a double slope, which converter is provided with first input means for receiving the analog voltage signal emitted by the transducer, second input means for receiving a reference voltage signal from which a predetermined maximum voltage signal is derived, integrator means operating sequentially to integrate a first signal value corresponding to the difference between the derived maximum voltage signal and the received analog signal during a predetermined period of time and after the expiration of the voo After a certain period of time, to integrate a second signal value corresponding to the sum of the first integrated signal and the reference signal, comparators configured to receive the integrated signals for effectively varying the integration time period of the second signal value until a predetermined 7905747 certain threshold level has been reached between the output of the integrator means and the reference signal and signal emitting means for transmitting a digital output signal derived from a accumulating digital count related to the time course of the variable time period, and consumables for receiving the broadcast signal from the signal broadcasters. System according to claim 9, characterized in that the converter integrators operate in a non-reversal mode. System according to claim 10, characterized in that the comparator effectively varies the variable time period in proportion to the level of the received transducer signal. System according to claim 11, characterized in that the converter integrating means is operative to integrate the first signal value in a polarity direction opposite to the polarity of the received reference signal. System according to claim 12, characterized in that the predetermined period of time of the converter integrators consists of an even multiple of the power line frequency with which the system is used. * System according to claim 12, characterized in that linearity means are operable to correct non-linearity in the digital count from which the output signal of the signal emitting means is derived. System according to claim 12, characterized in that the transducer is temperature sensitive for transmitting an analog signal in connection with the temperature of the measured gear. System according to claim 12, characterized in that the transducer is pressure sensitive for transmitting an analog signal in connection with the pressure of the measured state. System according to claim 9, 13, 14, 15 or 16, characterized in that the user members consist of a digital display member. 18. Linearization system for the digital output of a dual slope analog / digital converter, characterized in that a variable frequency clock is present, as are means for driving the clock during the fixed time period of 7905747 χ. * / 15 V * the converter at a frequency consisting of an even multiple of the power line frequency at which the converter operates and to drive the clock during the variable time period at controlled changes in frequency per unit time in accordance with the 5 linearity of the analog signal received by the converter. System according to claim 18, characterized in that a programmable read-only memory (PROM) is programmed to perform the clock frequency changes during the variable time period. 20. Device substantially as described in the description and / or shown in the drawing. 7905747