GB2036982A - Electrical impedance ratios - Google Patents

Abstract

The ratio of electrical impedance Z1 to Z2 is derived by applying simultaneously in repetitive sequence the outputs of generators 14 and 16 having amplitude voltages respectively of V1 and V2. V1 is a reference value and V2 is derived from a difference or error signal at error amplifier 6. The circuit is such that at balance <IMAGE> To reduce the effect of transients, the circuit can be arranged so that only a central part of the repetitive output of error amplifier 6 is used by detector 8. The circuit is particularly suitable for measuring capacitance ratios. In Fig. 4 (not shown) the sum of a plurality of capacitances is compared with a reference capacitance. In Fig. 5 (not shown) a multiplicity of capacitances are sequentially compared. <IMAGE>

Description

SPECIFICATION Electrical impedance ratios This invention relates to the measurement of electrical impedance ratios.

According to the invention there is provided an electrical apparatus for measuring the ratio of first impedance means Z1 and second impedance means2, comprising first and second impedance means connected to an input of direct current error signal measuring means, a first waveform generator connected to the first impedance means for providing a repetitive waveform at an amplitude corresponding to a reference d.c.

voltage V1, detector circuit means arranged to respond to an error output signal of said error measuring means and to generate a d.c. voltage V2 dependent thereon, a second waveform generator connected to said second impedance means for providing a repetitive waveform at an amplitude corresponding to voltage V2, and a synchronising circuit arranged to control said first and second waveform generators and said detector circuit, the arrangement being such that the ratio of Vr to V2 equals the ratio af Zl to Z2.

Electrical apparatus in accordance with the invention can provide a simple, convenient and accurate means of measuring the ratio of two electrical impedances. With apparatus in accordance with the invention it is possible accurately to convert the ratio of two electrical impedances to a ratio of two DC voltages, such conversion having good immunity to stray impedances, good linearity and low drift errors.

The first and second impedances may be of any type, but the apparatus in accordance with the invention is particularly suited where the first and second impedances are capacitive in nature.

For simplicity and accuracy, said first and second waveform generators comprise choppers providing first and second square waves. As preferred said first and second waveform generators comprise FET switches controlled by a common oscillator; this ensures the amplitude of the square waves are equal to the level of the DC voltages and that no offset voltages arise.

As alternative arrangements, said waveform generators may comprise sinewave generators or ramp generators.

Said error measuring means may provide a high overall gain and a virtual earth at its input. In some applications said error measuring mean and said detector means may comprise a single stage amplifier or may comprise a series of stages.

Said error measuring means and said detector means preferably comprises three principal stages: an intial amplifying stage, a detecting stage, and a stage providing said second DC voltage. The input impedance and gain of the initial amplifying stage may be selected to be appropriate for the values of the impedances to be compared.

Said detecting means is preferably driven synchronously with said first and second waveform means such as to detect only predetermined occurrence or phase intervals of the waveforms of error signals. Where the first and second waveforms are square waves, said detecting means preferably provides a path for detecting an intermediate part of one phase of each square wave and an inverting path in which an intermediate part of the other phase of the square wave may be detected; the detected parts of the square waves being used with the same sign to provide said second DC voltage stage. By detecting only intermediate parts of the square waves or other waveforms, the effect of stray impedances and non-linearities arising from active elements on the measurement is reduced, and an input to provide said second DC voltage means is substantially linear.In order to balance the input providing the second DC voltage means, a balancing circuit is preferably provided for periods when neither path of the detecting means is operative.

Where said waveforms are in the form of sinewaves or ramps, said detecting means may comprise a suitable analogue multiplier.

The second DC voltage stage preferably comprises an amplifier with high gain having a capacitance connected in known manner between the amplifier input and output. The integrating circuit responds to the signal from the detecting circuit, which is free of non-linearity and is substantially linear. The integrating circuit serves to reduce loop ripple in the apparatus. The gain of such integrating amplifier may be very much greater than that of the initial amplification stage and may provide most of the gain of said amplifier means, since it is easier and less expensive to provide high gain at DC than at the frequency of said first and second waveforms.

In addition to measuring a straightforward ratio of two impedances, the apparatus of the present invention may be employed to measure differential impedance ratios in the form

In this case, a third DC voltage V3 is provided, with a DC voltage equal but opposite in value to said first DC voltage. Said second waveform generating means is arranged to apply to said second impedance (Z2) a square wave having an amplitude equal to V2 - V3. The first waveform generating means is arranged so that square wave applied to the first impedance (Z,) having an amplitude equal to V2 + V,.

As a further possibility said first impedance means may comprise a plurality of impedances connectable in various ways so that their sums of differences can be compared with the second impedance means. That is multiplexing arrangements may be provided, in which case different sets of first and second impedances means are sequentially presented to the input of said error signal measuring means by suitable electrical gating arrangements.

Preferred embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a first embodiment together with a waveform diagram; Figure 2 is a more detailed circuit diagram of the embodiment of Figure 1; Figure 3 is block diagram of a second embodiment of the invention for measuring differential impedances; Figure 4 is a block diagram of a third embodiment of the invention for comparing the sum of a plurality of impedances with a reference impedance; and Figure 5 is a block diagram of a fourth embodiment of the invention incorporating a multiplexing arrangement for sequentially measuring ratios of a multiplicity of impedances.

Referring to the first embodiment shown in Figure 1, a first variable impedance Z to be compared with a second impedance Z2 are connected to the input of amplifier means 4 comprising an error signal measuring amplifier 6, a synchronous detector circuit 8 and an integrating amplifier 10, amplifier 10 serving to provide gain and filtering against loop ripple.An oscillator 12 is arranged to provide control signals to detector 8 and to first and second waveform generators or choppers 1 4 and 1 6. Chopper 14, responsive to a first reference DC voltage V, provided by a source 18, provides a square wave to impedance Z1 having an amplitude corresponding to voltage V. Chopper 1 6 responsive to a second DC voltage V2 provided at the output of integrator 10, provides a square wave to impedance Z2 having an amplitude corresponding to voltage V2. For circuit balance it thus follows

Referring to the more detailed circuit diagram shown in Figure 2, impedances Zr, Z2comprise capacitances C1, C2 (e.g. capacitive transducers).

Chopper 14 comprises two FET switches F2, F2 controlled by drive A from the oscillator 12 (see the wave form diagram). An inverting amplifier 1, inverts the drive to F1 whereby impedance C, is grounded in the internal V, is not applied to C" so that F, is driven in antiphase to F2. Chopper 16 is similar in construction and comprises two FET switches F3, F4 controlled by drive A, and an inverting amplifier 12 ensures C2 is grounded in the intervals V2 is not applied to C2, so that F3 is driven in antiphase to F4.

Error signal measuring amplifier 6 comprises a first charge amplifier 20, having a capacitor C3 thereacross and being connected to an AC amplifier 22. Detector circuit 8 comprises two paths or channels, a normal channel 24 and an inverting channel 26, together with a balancing channel 28. Inverting channel 26 includes an inverting unity gain amplifier 30. The channels comprises a series resistor R and FET switches F,-, F2+, F,-, F2-, and F,B, F2B.Switches F,+, F2 are driven by drive B from oscillator 12, switches F1 Ft- are driven by drive D from oscillator 12 and switches F1B, F2B are driven by drive C from oscillator 1 2. it may be seen from the waveform diagram, normal channel 24 is operative to detect central portions of the high parts of the square waves provided by the choppers 14, 1 6 and inverting channel 26 is operative to detect central portions of the low parts of the square waves provided by the choppers 14, 1 6. Balancing channel 28 is operative during the intervals channels 24, 26 are inoperative and therefore a constant resistance R is presented to the input of integrator 10.

By partial detection, using of only the central parts of the square waves, non-linearities caused by active elements are removed, and time is permitted for stray capacitances Csx, C to become fully charged from the choppersource resistance. Thus stray capacitances Csx, Csv may vary without affecting performance, capacitances CsX, C connected at nodes X, Y being the main sources of stray capacitance. Another source of stray capacitance C is connected at node Z at the input to amplifier 20. However, since amplifier 20 provides a virtual earth at its input, Csz is not effective to affect the impedance measurement.

The presence of a constant resistance R at the integrator input ensures only a constant offset voltage may be introduced into the detector signal.

Integrator 10 comprises an amplifier 40 having a capacitor 42 thereacross. The integrator is arranged to provide most of the gain of the loop.

An additional filtering amplifier 44 may be provided if desired, but the integrator provides a convenient means of stabilizing the loop and filtering the output. Any additional filtering must meet the normal conditions for stability of feedback systems. The integrator also provides a convenient point for introducing a zero trim into the circuit. The time constant of the circuit is given by RC42/AEAD where AD is the detector gain, AE the error amplifier gain (in turn dependent on C" C2 and the gain of AC amplifier 22). The integrator drift is divided by the factor AEAD.

One specific embodiment of the circuit of Figure 2 gave the following performance: Output 0 10 V, bandwidth 75 Hz Residual non-linearity better than + 2 x 10-5 of F.S.D.

Zero drift 2 x 10-60f FSD per degree C Slope drift not measurable Carrier frequency 1 6 KHz Loop gain 106 at DC Referring now to the embodiments shown in Figures 3, 4 and 5, these are block diagrams only and precise circuit diagrams are not given, it being be understood that specific circuit diagrams may be derived from the diagram of Figure 2.

In the second embodiment of Figure 3, the object is to measure the differential impedance of two impedances, shown as two variable capacitor transducers having values C + AC, C - AC, the differential impedance ratio being [0+ AC(CAC)/[C + AC + CAC] = AC/C. In this second embodiment, parts similar to the first embodiment are indicated by the same reference numeral. In addition, a voltage source 50 is provided providing a third DC voltage, equal and opposite in value to the first DC voltage provided by the source 18. An array of FET switches F31, F32, F33, F34 is arranged to chop into square waves the first and third voltages from sources 18 and 50, together with the second DC voltage from the output of integrator 10.Whereas in the first embodiment FET switches connect the impedances under test to ground during intervals in which the DC voltages are not applied to the impedances, in this embodiment both test impedances are connected to the second DC voltage from integrator 10 via F32, F33 during the intervals in which the first and third voltages are not being applied to respective impedances C + AC, C - AC via switches F31, F34.

Figure 4 shows an arrangement for addition and subtraction of a plurality of capacitors and for the comparison of the sum with a reference capacitor CR. As shown an arrangement of FET switches F41-F44 and inverters 13, 14 chop the first DC voltage V1. FET switch F41 connects impedances CVI, Cv2, to V1 and switch F42 connects impedances Cvi, Cv2.... to ground in the intervals F41 is off. Switch F43 connects impedances.... Cvn-1, Cvn to V1 in antiphase with F41, and switch F44 connects impedances .....

Cvn-1, Cvn to ground in antiphase with F42 when F43 is off. Integrator output V2 is applied to reference impedance CR via chopping FET switches F45, F46 In,this case

Figure 5 discloses a multiplexing arrangement wherein impedances CVI, Cv2 Cvn are sequentially compared with reference capacitors CR1 CR2 ...... CRn Each capacitor cv1 corn has a respective chopper arrangement 114, 11 6, 214, 216, n14,nl6providinga square wave varying between ground and the first or second DC voltage. Chopper pairs 1 14, 1 16 .... n14, n16 are sequentially enabled in a multiplexing cycle by gates G1..... Gn to provide successive comparisons of capacitor pairs Cv1, CB1...... CVn' CRne It may thus be seen there has been disclosed simple and effective apparatus for measuring impedance ratios as a ratio of two DC voltages, which apparatus has good immunity to stray impedances, good linearity and low drift errors.

Claims (5)

1. Electrical apparatus for measuring the ratio of first impedances means Z1 and second impedance means Z2 comprising first and second impedance means connected to an input of direct current error signal measuring means, a first waveform generator connected to the first impedance means for providing a repetitive waveform at an amplitude corresponding to a reference d.c. voltage V1, detector circuit means arranged to respond to an error output signal of said error measuring means and to generate a d.c.

voltage V2 dependent thereon, a second waveform generator connected to said second impedance means for providing a repetitive waveform at an amplitude corresponding to voltage V2, and a synchronising circuit arranged to control said first and second waveform generators and said detector circuit, the arrangement being such that the ratio of V1 to V2 equals the ratio of Z1 to Z2.

2. Electrical apparatus according to Claim 1, in which said synchronising circuit is arranged to control said detector circuit to detect only a predetermined intermediate part of each occurrence of said error output signal.

3. Electrical apparatus according to Claim 1 or Claim 2, for measuring differential impedance ratios of first and second impedance means in which said first waveform generator is arranged to provide a waveform at an amplitude corresponding to V2 + V1 and said second waveform generator is arranged to provide a waveform at an amplitude corresponding to V2 -V1, such that the ratios of

equals

4. Electrical apparatus according to Claim 1 or 2, in which said first and/or second impedance means comprise a plurality of discrete impedances and there is provided circuit switching means for connecting said discrete impedances in predetermined combinations to form said first and/or said second impedance means.

5. Electrical apparatus for measuring ratios of impedances subsfantially as herein described with reference to the accompanying drawings.