SU1553918A2 - Digital phase meter - Google Patents

Abstract

The invention relates to a measurement technique and can be used to create high-speed high-precision digital phase meters, as well as high-precision phase-to-code converters for control digital computing systems. The purpose of the invention is to increase the frequency range of the input signals while maintaining the accuracy of measuring the phase shift for a given discharge grid of counters. The goal is achieved by the introduction into the device according to auth. N 1406515 of the third counter, read-only memory, register and frequency divider. 1 il.

Description

The invention relates to a measurement technique and can be used to create high-speed digital phase meters of increased accuracy, as well as high-precision phase-to-code converters for control digital computing systems.

The purpose of the invention is to increase the frequency range of the input signals while maintaining the accuracy of the phase shift measurement for a given discharge grid.

The drawing shows a block diagram of a digital phase meter.

The digital phase meter contains 1 clock pulse generator, synchronization unit 2, the first 3 and second 4 counters, the first 5, the second 6, the third 7, the fourth 8 and the fifth 9 elements And, the first 10, the second 11 and the third 12 triggers, the first 13, the second 14, the third 15, the fourth 16, the fifth 17 and the sixth 18 pulse formers, the first element OR 19, the fourth 20, the fifth 21, the sixth 22, the seventh 23, the eighth 24, the ninth 25 and the tenth 26 triggers, the second 27 , third 28 and fourth 29 elements OR, element OR-NOT 30, sixth element AND 31, generator of 32 pulses, seventh driver of 33 pulses, eleven trigger 34, pulse distributor 35, first limiting amplifier 36, first comparator 37, second limiting amplifier 38, second comparator 39, third counter 40, read-only memory (ROM) 41, register 42 and frequency divider 43, the first the output of the generator 1 clock pulses connected to the second input of the fourth element And 8 and the first input of the third element OR 28, the second input of which is connected to the second input of the first element And 5 and the second output of the generator 1 clock pulses, the third output kooi

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00

Yu

one

Secondly, it is connected to the clock input of the third counter 40, the fourth output of the generator 1 of clock pulses is connected to the second input of the frequency lecturer A3, the first output of the synchronization unit 2 is connected to the information inputs of the trigger 10, 21 and 22, the second output to the installation of the O counters 4 and the AO , the third output to the inputs of installation O of the seventh trigger 23 and the first counter 3, the fourth output to the input of installation O of the ninth trigger 25, the fifth output to the inputs of installation O of triggers 20, j 21 and 26, the synchronization input of the eleventh trigger 34 ow by the input block and 2 synchronization and the third input 44 of the digital phase meter, its inverted output is the first output of the unit 2

2 synchronization and connected to the second input of the pulse distributor 35, the first, second, third, fourth outputs of which are respectively the second, third, fourth and fifth 2 outputs of the synchronization unit 2, the fifth output of the pulse distributor 35 is connected to the installation input O of the eleventh trigger 34 , whose information input is connected to the bus with level 1, the first input of the distributor

35 pulses are connected to the output of the third element OR 28 and the synchronization input of the second counter 4, the output of the first element OR 19 is connected to the synchronization input of the first counter 3, the enable input of which is connected to the forward output of the eighth trigger 24 and the first input of the OR-HE element 30, input enable the second counter 4 is connected to the direct output of the seventh trigger 23, the resolution input of the third counter 40, the synchronization input of the eighth trigger 24, the second input of the element OR NOT 30, the outputs of the first

3 and the second 4 counters are respectively the first 45 and second 46 outputs of the digital phase meter, the direct output of the first trigger 10 is connected to the first input of the first element AND 5, the output of which is connected to the second input of the first element OR 19, the first input of the second element And 6 is connected to the output of the third driver 15, the synchronization input of the first trigger 21, the first input of the third element

And 7, the information input of the second trigger 11 is connected to its inverse output and the second input of the second ele3

four

four

five

five

0

0

five

0

five

0

five

And 6, the output of which is connected to the second input of the fourth element OR 29, the output of the fifth trigger 21 is connected to the second input of the third element And 7, the output of which is connected to the synchronization input of the second trigger 11, the direct output of the third trigger 12 is connected to the first input the fourth element AND 8, the output of which is connected to the first input of the first element OR 19s, the second input of the fifth element AND 9 is connected to the direct output of the second trigger 11, the output of the fourth pulse shaper 16 is connected to the first input of the fifth element And 9, the output of which It is connected to the second input of the second element OR 27, the output of the sixth pulse generator 18 is connected to the second input of the sixth element AND 31 and the synchronization inputs of the first 10 and sixth 22 triggers, the output of the second element OR 27 is connected to the input of the O installation of the first trigger 10, the inverse output of which connected to the synchronization input of the fourth trigger 20, the direct output of the sixth trigger 22 is connected to the first input of the sixth element I 31 and the information input of the third trigger 12, the output of the installation O of which is connected to the input of the installation O, in of the seventh trigger 24 and the output of the fourth element OR 29, the output of the fifth pulse shaper 17 is connected to the synchronization input of the third trigger 12, the inverse output of which is connected to the synchronization input of the tenth trigger 26, the first limiting amplifier 36 is connected to the input of the first comparator 37, the output which is connected to the inputs of the third 15 and fourth 16 pulse shapers, the output of the second amplifier-limiter 38 is connected to the input of the second comparator 39, the output of which is connected to the inputs of the fifth 17 and sixth 18 impu drivers The inputs of the first 36 and second 38 limiting amplifiers are the inputs of the first 13 and second 14 pulse shapers and, respectively, the first 47 and second 48 inputs of the digital phase meter, the forward outputs of the fourth 20 and tenth 26 triggers, respectively, are connected to the first inputs of the second 27 and the fourth 29 elements OR, direct, the output of the ninth trigger 25 is connected to the input of the installation About the sixth trigger 515

Gera 22, the information input of the seventh trigger 23 is connected to its inverse output, the first and second outputs of the seventh imaging unit 33 are the first and second outputs of the clock generator 1, respectively, the first and second outputs of the generator 32 pulses are the third and fourth outputs of the generator 1 clock pulse, the output of the third counter 40 is connected to the first input of the persistent storage device 41, the second input of which is connected to the second input of the register 42 and is the fourth input 49 (Digit mode A new phase meter, the output of a permanent memory device is connected to the first input of register 42, the output of which is connected to the first input of frequency divider 43, the input of the seventh pulse maker 33 is the input of clock generator 1 and the output of the sixth element And 31 is connected to the synchronization input of the seventh trigger 23, the output of the element of the IPI-NE 30 is connected to the synchronization input of the ninth trigger 25, to the information inputs of the fourth 20, eighth 24, ninth 25, twenty-six triggers connected and with a level of 1.

Digital phase meter works as follows.

Sinusoidal or rectangular voltages are supplied to the first 47 and second 48 inputs of the digital phase meter, with the voltage across the voltage 47 being the information signal. The input signals, passed through the first 36 and second 38 limit amplifiers, are amplified and symmetrically limited in amplitude. Using the first 37 and second 39 comparators, the input signals are converted to square voltage with levels compatible with the levels of the series of chips used. Fifth 7 and iesta 18 pulse formers generate pulses that are associated respectively with the falling and leading edges of the reference signal.

In the initial period of the circuit, the eleventh trigger 34 starts from input 44. The eleventh trigger 34 generates an interval with a level O, which removes the prohibition from the second input of the distributor 35 impulse, resulting in

186

Outputs Tin Prednogo develops pulse control pulses. In the case of pulses, the PULSES from the output of the third element OR 28 arrive at the first input of the distributor 35 pulses, at the outputs of which a sequence of pulses begins to be generated.

Impulse from the first output zeroed the second 4 and third 40 counters, and impulse from the second output - the seventh trigger 23 and the first counter 3. The impulse from the third output embraced the ninth trigger 25, the impulse from the fourth exit - the fourth 20, the fifth 21 and the tenth 26 triggers. The pulses from the fifth output of the distributor 35 and the pulses at the output of the eleventh flip-flop 34 sets a level 1, disrupting the operation of the distributor 35 pulses and arriving at the information inputs of the fifth 21, first 10 and sixth 22 flip-flops.

The process of measuring the phase shift takes place in two stages. At the first stage, depending on the frequency of the input signal, the frequency of the resolution resolution intervals is determined. At the second stage, the phase shift of the input signal and the period of the reference signal are measured.

First stage. After zeroing the third counter 40, the interval from the direct output of the seventh trigger 23, corresponding to the reference signal period, arrives at its resolution input. The clock input of the third counter 40 receives the frequency f ,, at the output of which a digital code is generated, corresponding to the reference signal period. This code is sent to the first input of the ROM 41 as an address. By the Mode command, the division factor K | is selected from the fourth input 49 of the digital phase meter at this address. and is rewritten into register 42. From the output of register 42, the division factor is fed to the first input of the frequency divider 43, the second input of which receives the frequency f from the generator of 32 pulses. In the frequency divider 43, the frequency f is divided by the K factor. The divided frequency does not come from the driver 33 as a reference frequency.

If the frequency of the input signal decreases, i.e. the period of the input signal increases, the frequency fj from the generator of 32 pulses fills

five

ten

a longer resolution interval, ready to go to the third counter 40. The ROM 41 receives the address at which the division factor Kf with a larger numerical value is selected. From the frequency divider 43, the filling frequency is less than the filling frequency. Before reducing the purity of the input signal, neither the driver 33 enters, from where it goes to counters 3 and 4. Thus, the effect of the correction circuit collected by the NTS to the third counter 40, the ROM 41t register 42, the frequency divider 43, allows It does not change the frequency of the filling, which arrives at the counters in accordance with the change in the frequency of the input and reference signals, keeping the relative error at a constant level. An increase in the accuracy of the digital phase meter offered in comparison with the known one occurs due to the use of all bits of the bit.

This is followed by the main step - 25 of measuring the phase shift of the input signal relative to the reference.

The third 15 and fourth 16 pulse shapers produce impulses,

15539188

The horn of the trigger 11 level 1, which allows the pulse from the output of the third pulse generator to pass through the second element 6, the fourth element OR 29 to the input O of the third trigger 12, prohibits its operation. By this, the end of the interval is formed, which arrives at the fourth element And 8. The tenth 26 and fourth 20 triggers allow the third 12 and first 10 triggers to generate their intervals only once during a single phase measurement. This is achieved by the fact that at the end of the intervals generated by the third 12 and first 10 triggers, the inverse outputs of these triggers will have a positive differential arriving at the sync inputs of the tenth 26 and fourth 20 triggers, which at the outputs of these triggers set level 1, which through the fourth 29 and second 27 elements OR prohibits further switching of the third 12 and first 10 flip-flops before the beginning of the next phase measurement phase. From the first generator output 1 clock pulses to the second input of the fourth

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tied respectively to the front element AND 8 enters the sequence and the falling edge of the input signal. The impulse from the third imaging unit 15 of the pulses arrives at the first input of the second element I 6, and the impulse from the fourth imaging device 16 pulses - at the first input of the fifth element I 9.

pulses, which fills the interval formed by the third trigger 12 and arriving at the first input of the fourth element OR 29. From the second output of the 1 clock pulse generator, the pulse sequence is shifted by half a cycle relative to the sequence at the first clock pulse 1 generator output the input of the first element And 5 and fills the interval formed by the trigger 10. The intervals filled with pulses from the outputs of the fourth 8 and first 5 elements And go to the first and second inputs of the first second OR gate 19. Since the pulses are filled in the slots spaced by half the period, the area of overlap of intervals is noted doubling pulse repetition frequency. The pulse sequence from the output of the first element OR 19 is fed to the synchronization input of the first counter 3, at the output of which a code is obtained that corresponds to the product of the double phase shift (2) between the reference and input signal by the frequency coefficient (Kf). On the second counter 4, because the frequency of the counting pulses

The first pulse from the output of the third driver 15 pulses, arriving at the synchronization input of the fifth trigger 21, sets its output level 1, which allows the pulse from the output of the third driver 15 pulses to pass through the third element And 7 to the synchronization input (second trigger) 11 and sets at the direct output of the second trigger 11 a level 1, which allows the pulse to pass from the output of the fourth driver 16 pulses through the fifth element AND 9 and the second element OR 27 to the input of the installation O of the first trigger 10 and cf Vaeth its operation to form the end of the interval, input to the first input of the first AND gate 5. A second pulse from the output of the third shaper 15, entering through a third AND gate 7 to the clock input of the second flip-flop 11 sets the output to Auto iyversnom

Element And 8 enters a sequence

pulses, which fills the interval formed by the third trigger 12 and arriving at the first input of the fourth element OR 29. From the second output of the 1 clock pulse generator, the pulse sequence is shifted by half a cycle relative to the sequence at the first clock pulse 1 generator output the input of the first element And 5 and fills the interval formed by the trigger 10. The intervals filled with pulses from the outputs of the fourth 8 and first 5 elements And go to the first and second inputs of the first second OR gate 19. Since the pulses are filled in the slots spaced by half the period, the area of overlap of intervals is noted doubling pulse repetition frequency. The pulse sequence from the output of the first element OR 19 is fed to the synchronization input of the first counter 3, at the output of which a code is obtained that corresponds to the product of the double phase shift (2) between the reference and input signal by the frequency coefficient (Kf). On the second counter 4, because the frequency of the counting pulses

Twice as high as when the phase was counted, a code is generated that corresponds to the product of the double period (2P) of the reference signal and the frequency coefficient (K-). The obtained codes 2уКс and 2Р-К ,, respectively, from the first and second outputs of the digital phase meter, go to a device that calculates the angle (V1) corresponding to the phase shift between the reference and input signal

Claims (1)

 Thus, from this formula, it is clear that q (depends only on y and P and does not depend on the frequency of the input signal, since the coefficient Kp, which depends on the frequency of the input signal, decreases. Therefore, the accuracy of the determination is determined only by a discharge grid the counter, and it is constant for all frequencies of the input signals. Digital phase meter auth. St. No. 1406515, different Q five 0 5 In order to increase the frequency range of the input signals while maintaining the accuracy of measuring the phase shift for a given bit grid of counters, a counter, a permanent memory, a register, a frequency divider are entered into it, the output of the seventh trigger is connected to the counter input of the counter, the second output the synchronization unit is connected to the reset input of the counter, the clock input of which is connected to the third input of the clock generator, the fourth output of the clock generator is connected to the second input of the clock divider The output of the counter is connected to the first input of a permanent storage device, the output of which is connected to the first input of the register, the second input of which is connected to the second input of the permanent storage device and is the fourth input of the digital phase meter, the output of the register is connected to the first input of the frequency divider, the output which is connected to the input of the clock generator. IS-YUI