SU1628013A1 - Capacitance-to-frequency converter - Google Patents

Abstract

The invention relates to measurement technology and can be used to measure capacitances in electrical circuits. The purpose of the invention is to improve the accuracy and expand the scope. The conversion algorithm is set by the control unit 1 and determined by the operation cycle of the keys 22 and 23. The reference frequency generator 10 generates square pulses that determine the counting mode of the logical states of the trigger 11 and the counter 12. The output signals of the triggers 13 and 14, which are synchronized using a differentiating circuits 15, diode 16 and resistor 18, control the operation of switches 3 and 4, connecting

Description

This invention relates to a measurement technique and is intended to measure capacitors in electrical circuits.

The purpose of the invention is to improve the accuracy and expand the scope.

Figure 1 shows the block diagram of the capacitance-to-frequency converter; 2 shows timing diagrams for his work.

The capacitance-to-frequency converter contains a control unit 1, a voltage source 2, switches 3 and 4, a measured and exemplary capacitors 5 and 6, a charge amplifier 7, a controlled detector 8 and a trigger 9. The output of a source 2 reference the voltage is connected to the second (informational) input of the switch 3 and the second (informational) input of the tator 4, the first (informational) input of the switch 3 and the first (informational) input of the switch 4 are connected to the common bus of the capacitor-to-frequency converter. The outputs of the switches 3 and 4, respectively, through the measured and exemplary capacitors 5 and 6 are connected to the input of the charge amplifier 7, the output of which is connected to the first (control) input of the trigger 9 through the controlled detector 8 and the second (clock) input to the third the input (control) of the switch 3 and with the second output of the control unit 1. The third input (control) of the switch 4 is connected to the first output of the control unit 1.

The third and fourth outputs of control unit 1 are connected respectively to the second and third inputs (controls) of the controlled detector 8. The inverse output of the trigger 9 is the output of the capacitance-to-frequency converter and connected to the input of the control unit 1. The control unit 1 comprises a reference frequency generator 10, the output of which is connected to the counting inputs of the trigger 11 and the counter 12 with the decoded outputs. The inverse output of the trigger 11 is connected to the counting input of the trigger 13, the forward output of the trigger 11 is connected to the counting input of the trigger 14, the forward output of the trigger 13 is the first output of the control unit 1, the forward output

the trigger 14 is the second output of the control unit 1 and through the differentiating circuit 15 is connected to the anode of the diode 16 and the first input of logic element 2IL 17. The diode 16 cathode is connected to the setup input of the zero state of the trigger 13 and through the resistor 18c to the common bus of the converter of the capacitor to frequency . The first input of the logical element ZILI-NOT 19 is the input of the control unit 1, the second and third inputs of the element ZILI-NOT 19 are connected respectively to the inverse outputs of the trigger 13 and 14. The output of the logical element ZILI-NOT 19 is connected to the second input of the logical element 20 element 2ILI17, the output of which is connected to the input of the installation in the zero state of the counter 12c decrypted outputs, and the output of the counter 12 with the decoded outputs corresponding to its zero state is the third output of the control unit 1 And the output corresponding to the second state of the counter 12 is the fourth output of the control unit 1.

The controlled detector 8 contains a capacitor 21, the first terminal of which is the first (informational) input of the controlled detector 8, the second terminal of the capacitor 21 is connected to the moving contacts of the keys 22 and 23. Fixed, the contact of the key 22 is connected to the first output of the capacitor 24 and the inverting input an operational amplifier 25, the non-inverting input of which is connected to the second terminal of the resistor 26 and the fixed contact of the switch 23 connected to the common bus. The output of the operational amplifier 25 is connected to the second output of the capacitor 24 and the anode of the diode 27, the cathode of which is connected to the first output of the resistor 26 and is the output of the controlled detector 8. The control inputs of the keys 23 and 22 are the second and third inputs of the controlled detector 8.

Converter capacity to frequency works as follows.

The operation algorithm is set by the control unit 1 and determined by the operation cycle of the keys 22 and 23. At the output of the reference frequency generator 10. The frequency of which is stabilized by a quartz resonator, square pulses are formed (the output voltage of the generator 10 is shown in Fig. 2.1). This signal sets the counting mode of the logic states of trigger 11 and counter 12 with decrypted outputs. The output voltage of the trigger 11 is shown in Fig. 2.2. The device implemented on the flip-flops 13 and 14 is a digital phase shifter that provides a phase shift value between the output voltages of the flip-flops 13 and 14 equal to p 90 °. The output voltage on the direct outputs of the flip-flops 14 and 13 are respectively shown in FIG. .2 3 and 2.4. The capacitance-to-frequency converter operation is synchronized by the voltage taken from the output of the trigger 14. The trigger 13 is synchronized by a reset device, which is redacted using the differentiation circuit 15 of the diode 16 and the resistor 18. The diode 15 is designed to eliminate the negative voltage generated as a result of differentiation of the output signal of the trigger 14. The voltage at the input of the installation to the zero state of the trigger 13 is shown in Fig. 2.5. The output signals of the flip-flops 13 and 14 control the operation of the switches 3 and 4. Consequently, rectangular-shaped voltages with an amplitude U0 synchronously with the output voltages of the flip-flops 13 and 14 are formed on the measured and reference capacitors 5 and 6. The measured and reference capacitors 5 and b are connected to the source 2 of the reference voltage only when a logical unit signal is applied to the third input (control) of the switches 3 and 4. As a result of this synchronization, a voltage is formed at the output of the charge amplifier 7, shown in Fig. 2.b. As a result of switching the keys 22 and 23 (the voltages applied to the control inputs of the keys 22 and 23 are shown at 2.9 and 2.10, respectively), performed when the logic unit signals are fed to the control inputs of the keys 22 and 23 according to the algorithm specified by the operation of the counter 12 s by decoded outputs, balancing the transform of the capacitance to frequency is achieved. When the voltage level at the output of the controlled detector 8 (Fig. 2.7) is less than the threshold voltage, the trigger 9 is triggered. A signal of the logical unit is generated at its inverse output. The voltage at the inverse output of the trigger 9 is shown in Fig. 11.11. The output signal of the trigger 9, corresponding to a logical unit, forms the output of the logic element

ZILI-NOT 19 logical zero signal. In this case, the counter 12 with decrypted outputs is reset only by the signal taken from the output of the trigger 14. The signal generated at the installation input

in the zero state of the counter 12 with the decoded outputs, is shown in Fig. 2.8. In this case, the amount of charge formed on the capacitor 21, which is part of the controlled detector 8, is determined from the expression

021 Uo

K g

WITH

C21

de Co and Cx are, respectively, the capacitance values of the sample and measured capacitors 5 and 6;

Su is the capacitance value of the negative feedback capacitor of charge amplifier 7;

C21 capacitor capacitance

21;

Uo is the output voltage of the source 2 of the reference voltage ,.

In this case, the output voltage of the controlled detector 8 is imputed almost linearly stepwise, and the amplitude of the magnitude of one positive increment is determined from the expression

C y C 24

where C21.C24 is the capacitance values of the capacitors 21 and 24 included in the controlled detector 8.

When the output voltage of the controlled detector 8 reaches a value greater than or equal to the trigger voltage of the trigger 9, the trigger 9

Logical unit signal is recorded. This occurs synchronously with the logical unit level formed at the direct output of the trigger 14. Trigger 9 does not require the long-term stability of the threshold input trigger level D. At the inverse output of the trigger 9 at this time point, a logical zero signal is generated ZILI-HE 19, as well as the differentiating circuit 20, makes an additional installation in the zero state of the counter 12 with decrypted outputs. In this case, the operation cycle of the keys 22 and 23 is shifted by the duration of one period of the generator 10. In this case, the amount of charge generated on the capacitor 21 is determined from the expression

Q21 Uo (С о + С х) С 20

C y C 24

The magnitude of the magnitude of the negative increment at the output of the controlled detector 8 at this time point is determined by the expression

AUD Uo (C ° + Cx) C20

L y C 24

When the controlled detector 8 of a given increment value is subtracted from the output voltage and after the subsequent high logic level arrives from the output of the trigger 14, the trigger 9 is set to the zero state and a logical unit signal is generated at its inverse output. Thus, the whole process is cyclically repeated . In this case, the magnitude of the error, due to the discreteness of the increments of the output voltage of the controlled detector 8, accumulates on the capacitor 24 and, when the value of this sampling error is reached, additional triggering of the trigger 9 occurs. Thus, the output frequency is determined only by the capacitance Cx and Co and the value reference frequency

. C o - C x

1NYL I l, f

Co + C x

As the value of the exemplary frequency f 1, it is advisable to use the output frequency of the generator 10fo 4fi, where the coefficient 4 is due to the presence of flip-flops 13 and 14, as well as flip-flop 11. In the capacity-to-frequency converter, the output signal of the generator 10 is taken. frequency generator 10 is divided into 4 with the help of triggers 11,13 and 14. Therefore, the factor 1/4 is included in the function of converting the capacitor to frequency converter.

In view of the above, the conversion function takes the form

C o - C x

4 (Co + Cx)

This is true for the first measurement mode. When converting a capacitance transducer to a frequency in the mode of measurement, Cox is required. Swap the measured and exemplary capacitors (capacitor 6 becomes the measured capacitor, capacitor 5 is the exemplary capacitor).

In this case, the conversion function will take the form

f - fn С х - С о

feb (4 (with + s7u

The algorithm of operation of the converter capacity to frequency in this case is identical to the above algorithm.

Increasing the sensitivity of the conversion increases the resolution, which in turn leads to increased accuracy. Metrological studies carried out with a change in the capacitor Cx in the range of 0.41 - 12 pF, the value of the capacitance of the exemplary Co 13 pF capacitor and the oscillator frequency fo 50 kHz show that the magnitude of the reduced error does not exceed the value of 0.07% (a decrease of more than 2 times lower).

The use of a capacitance-to-frequency converter allows the linear characteristic of the conversion to be

when used with differential capacitive sensors of varying clearance, and with differential sensors with varying area of the plates, which expands its functionality.

Claims (1)

Claims: Capacitance-to-frequency converter containing a voltage source, first and second switches, measurable and exemplary capacitors, a charge amplifier, a trigger, a controlled detector and a control unit, the outputs of the first and second switches, respectively The first and second capacitors are connected to the input of the charge amplifier; the first input of the second switch is connected to the first input of the first switch and connected to the common bus of the converter; the second input of the first switch and the second information input of the second switch are connected to the output of the reference voltage source; yes it is connected to the first input of the controlled detector, the trigger output is connected to the input of the control unit, the first output of which is connected to the third input of the second switch, the second output of the block control connected to the third input the first switch, characterized in that, with a circuit for improving the accuracy and expansion of the field of application, the output of the controlled detector is connected to the first trigger input, the second input of which is keys to the second output of the control unit, the third and fourth outputs of which are connected respectively to the second and third inputs of the controlled detector.