SU1485385A1 - Pulse duration converter - Google Patents

Description

The invention can be used in devices for processing and generating pulse signals. The purpose of the invention is to increase the area 2

hardiness. The device contains a generator of 1 clock pulses, input buses 14, an element of OR-NOT 6, a converter of 5 codes, a divider of 3 frequencies, two counters 7 and 8 pulses, a block 9 of code comparison, trigger 10. Introduction of inverter 2, bus 15 of the initial state, multiplexer 4, the decoder 13 and the two flip-flops 11 12 ensure that no spurious signals are present at the output, either when noise appears on any of the input buses during the pauses of clock pulses and during the action of the clock pulses themselves. 2 Il.

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The invention relates to a pulse technique and can be used in devices for processing and generating pulse signals.

The purpose of the invention is to improve the noise immunity of the converter pulse duration.

FIG. ! The electric functional diagram of the device is presented; ; d in fig. 2 - time diagrams explaining his work.

The pulse duration converter contains a pulse generator 1, an inverter 2, a divider 3 frequencies, 15 multiplexer 4, a converter of 5 codes, an element of OR-NOT 6, counters 7 and 8 pulses, a block 9 of code comparison, three trigger 10-12, a decoder 13, input bus 14, bus 15 source-20, the output bus 16, and the input bus 14 is connected to the corresponding inputs of the element ILINE 6 and the converter 5 codes, the outputs of which are connected ^! with the corresponding control inputs of the multiplexer 4, the first information input of which is connected to the output of inverter 2, the gating input of the code comparison unit 9 and the input of the divider 3 are frequency 30, the second information input is with the first output of the frequency divider 3, the third information input is with the second output of the divider 3 frequencies, the first input of the decoder 13 and the counting input of the pulse counter 7, and the output with the counting input of the counter 8 pulses, the information inputs of which are connected to the corresponding buses 15 of the initial state, records - 40 with K — trigger input 12, K input of the pulse counter 7 and direct trigger output 10, and outputs with the first group of inputs of the code comparison block 9, respectively, the second group of 45 inputs of which is connected to the corresponding outputs of the counter of 7 pulses and the corresponding inputs the decoder 13, and the output with the K-input of the trigger 10, the 5-input of which is connected 50 with the inverse output of the trigger 11, and the inverse output with the second K-input of the trigger 11, the first K-input of which is connected to the output of the pulse generator 1 and the input inverter 2 and 55

8-input - with the output of the element OR-NOT 6, the output of the decoder 13 is connected to the 3-input of the trigger 12, the output of which is connected to the output bus 16. The construction of the frequency divider provides at its first output the frequency of the signal P / 2, and at the second output P / 3, where P is the frequency of the signal generator 1 pulses. The circuit for constructing the converter of 5 codes provides (for the case of three input signals) the implementation of the following expressions of the Boolean algebra __

1), = abc ν abs ν abc V abc;

() ₂ = abc ν abc ν abc ν abc,

where, (), 2 "signals at the output of the converter 5 codes; a, b, c ~ signals on input buses.

The device works as follows.

In the initial state, the tires 14 and the single outputs of the triggers 10 and 12 have a level of "0", the output of the OR-NOT 6 element, the inverse outputs of the triggers 10 and 11, the outputs of the multiplexer 4, the comparator 9 and the decoder 13 are level 1 , the counter 7 is set to zero, some small number is entered into the counter 8, for example 3. The binary code of this number is set permanently on the tires 15.

At the time point C, a signal is received via bus 14c (Fig. 2, c). If at this moment at the output of the generator 1 the level ”1” is in effect, immediately after the signal from the output of the element OR NOT 6, trigger 11 (Fig. 2, d) is switched, therefore, trigger 10, Level “O” from the inverse trigger output 10 is fed to the reset input of the trigger 11, and the single output of the trigger 10 removes the blocking of the counters 7 and 8 and the trigger 12 (figo 2, d). The multiplexer 4 is given the code 01, so the counting input of the counter 8 receives the frequency Р _о / 3. The same frequency arrives at the counter 7. After four pulses of наfig are received at the counter 7. 2, g) after time ~, the decoder ⁷ torus 13 is triggered and switches the trigger 12, while on the bus 16 the leading edge of the output signal is formed (Fig. 2, k).

At the time point, the bus 14c receives the second signal (Fig. 2.6), while the converter 5 issues a code 10, multiplexer 4 receives pulses with a frequency Р _о / 2 (Fig. 2, е) “Counter 8 counts faster to time point T. The bus 14a at the moment of time G _b (Fig. 2, a) receives the third signal, while the pre ^-

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Form 5 emits code 11, and the multiplexer transmits pulses with frequency E „.

At the moment of time, the signal from the bus 14a is taken, in the time interval between the moments and the counter 8 counts with the frequency Е _о / 2. At the moment of time the signal from the bus 14c is taken. In the interim, the count- | d

Chick 8 counts with frequency P / 3. At the moment of time b ₆ after the termination of the last signal on the bus 14c, the converter 5 outputs the code 00 and the multiplexer 4 is locked. By the time 15, a number proportional to the sum of the durations of the input signals on the tires 14a, hs accumulates in the counter 8 '. At time b ^, the output of the element OR NOT 6 is set to 20

level "1", so the trigger 11 switches to the zero state by the level "0" at the input

Counter 7 counts the pulses following with the frequency Γθ / З. By the time 25 ί _{Ί, the} codes of the counters 7 and 8 will become equal, the comparison block 9 will work and the level “0” will switch the trigger 10 to the zero state, by which the initial number from the tires 15 will be entered into the counter 8, and the counter 7 reset to zero. The trigger 12 switches to state "0", the signal on bus 16 ends. Thus, a signal is generated on the output bus ^ 5, the duration of which

* - Vshu ^e a ⁺ % ^{+ C} with '

where? „, 2 · ^, h _s - the duration of the input signals on the tires a, b, c.

In the case of a signal on one of the tires, for example, 14c, similarly, after the blocking is released, a certain number of pulses are inserted into the counter 8, corresponding to the duration of the input signal. At the end of the input signal, the multiplexer is locked, and the counter 7 continues to count until the codes are equal _. Next, the comparison block 9 is triggered and the circuit is returned to its original state.

When a short intermittent impulse arrives at the input during a pause from the generator 1, the trigger 1 1 does not switch because it is kept in the initial state by the level "0" at the input K ,. Therefore, trigger 10 also does not switch, counters 7 and 8 and

the trigger 12 remain blocked, the signal on the bus 16 is not formed

In the case of receipt at the moment b ₈ to one of them 14 impulse interference, during the pulse at the output of the generator I, the trigger 1 1 switches and switches the trigger 10, counters 7 and 8 and the trigger 12 are unlocked. The converter 5 codes will have time to issue a signal but the multiplexer 4 receives the level "0" from the output of the inverter 2, and the counting input of the counter 8 pulses do not pass ·. The counting input of the counter 7 receives pulses from the divider 3 frequency. When reaching in the counter 7 code equal to the code entered into the counter 8 bus 15 (for example, the number 3), the block 9 comparison and switches the trigger 10 to its original state. In this case, the decoder 13 does not have time to work and switch the trigger 12.

Thus, the device does not generate spurious signals at the output both when impulses appear on any of the input buses during the pauses of the clock pulses, and during the action of the clock pulses.

Claims (1)

Claim A pulse width converter containing a clock pulse generator, an output bus, three input buses, each of which is connected to the corresponding inputs of an OR-NOT element and a code converter, a frequency divider, the first output of which is connected to the C input of the first pulse counter, the outputs of which are connected to the first group of inputs of the code comparison unit, respectively, whose output is connected to the K input of the first trigger, and the second group of inputs to the corresponding outputs of the second pulse counter, which differs from o, in order to increase the noise immunity device introduced into it initial state code bus, second and third flip-flops, the multiplexer, the decoder and an inverter having an input connected to the output of the clock and the first K-input of the second flip-flop, and an output - to an input of 7 1485385 eight gating code comparison unit, the first data input of the multiplexer and the input of the frequency divider, the second output of which is connected with the secondary ring ₁ multiplexer input information, third information input of which is connected to the C-input of the first pulse counter and to the first input of the decoder, control inputs multi-) the typelexer - with the corresponding outputs of the code converter, and the output with the C-input of the second pulse counter, the information inputs of which are connected to the corresponding buses 1 the initial state code, and the recording input - with the K-input of the first counter, the K-input of the third trigger and the direct output of the first trigger, the inverse output of which is connected to the second K, -input of the second trigger, and 5-input with the inverse output of the second trigger, 5 - whose input is connected to the output of the element OR NOT, the outputs of the first pulse counter are connected to the corresponding inputs of the decoder, the output of which is connected to the 5-input of the third trigger, the output of which is connected to the output bus. 1 hour 146 14c eleven d 101 .-R ιτιιτίιιτι ^CHE I ι, Ι. I IIIIC Η IIIIIIIIIIIIII11111IIIII11 1111Ш11ИIII1Ц1 * h ; sixteen "E ~ Fm.g