SU1478339A2 - Device for checking monotonously varying code - Google Patents

Abstract

The invention relates to automation and computer technology and is an improvement of the invention according to author's certificate No. 1304174. Its use in a system that forms a monotonically varying code allows the functionality of the device to be expanded by providing self-monitoring modes and repeated repeated start-ups. The device contains 1.2 memory blocks, a comparator 3, information receiver 4, pulse generator 5, AND 6 element, start generator 7, OR 8 element and triggers 9, 10. Functional expansion is provided by the introduction of the HE element 11, AND 12 elements , 13, counter 14, block 15 And elements, block 16 decryption, switch 17 and shift register 18. 1 hp f-ly, 1 ill.

Description

The invention relates to automation and computer technology, can be used in a system that generates a monotonously changing code and is an improvement of the invention by ed. St. No. 1304174.

The purpose of the invention is the expansion of functionality by providing modes of self-control and repeated repeated start.

The drawing shows a functional diagram of the device.

A device for monitoring a monotonously varying code contains the first and second memory blocks 1 and 2, a comparator 3, an information receiver 4, a pulse shaper 5, a first AND element 6, a start generator 7, an OR element 8, the first and second triggers 9 and 10, the element NOT 11, the second and third elements And 12 and-13, the counter 14, the block And the elements 15, block 16 decryption, the switch 17 and the shift register 18. The drawing indicates the information input 19, the first, second and third control inputs 20-22 and control outputs 23.

The information receiver 4 is made on the switch 24, the element And 25, digital printing unit (CPU) 26 and the decoder 27.

In the shift register 18 with a clock bus (not shown), the first and third outputs are direct outputs of the first and last but one digits, and the second and fourth are inverse outputs of the second and last digits, respectively.

The device operates as follows.

The device can work with ’parallel, consecutive codes, arriving both high and low bits ahead. The device operates in three modes: in the mode of automatic control of a monotonous sequence of codes of the investigated source; in the current indicator mode. code values; in self-control mode.

In the automatic control mode, input 21 does not receive a signal, and through the OR 8 element, the triggers 9 and 10 are reset to zero only from the start generator 7. When the first pulse of the generator 7 arrives, the potential of the logical unit is set at the inverse output of the trigger 10, which allows the synchronization signals to pass from the pulse shaper 5 through the And element 6. The synchronization signals are generated by the pulse shaper 5, which can consist, for example, of a pulse counter, which counts the pulses of the reference generator, and a block of decoders that analyze the state of the counter. In the case of sequential codes, the synchronization signal is a pulse (word strobe) with a duration equal to the length of the controlled code word. These pulses are fed to memory unit 1 and comparator 3 for synchronous reception of codes from input 19 and comparison of the previous code in memory unit 1 and subsequent to input 19. In memory unit 2, for each comparison cycle, the compared code values are entered and stored until the next cycle, which are output to the information receiver 4. At a time when the compared codes are different from each other by more than a predetermined amount, for example, ± 1 discrete low-order digit, the comparator 3 generates a pulse that sets the trigger 9 in the state of a logical unit. In the general case, this pulse can be generated at any moment of time within the time interval corresponding to the length of the code word. On the trailing edge of the word strobe supplied to the trigger synchronization input 10 (inside the time interval of which a comparator pulse 3 is generated, the latter is set to a logic zero state at the inverse output). Thus, after this, the supply of pulses of the pulse shaper 5 through the And 6 element to the memory unit 2 is stopped and two full codes are recorded in it, at the time of comparison of which a failure occurred. By the code on the control inputs 20 (at the address) from the outputs of the memory unit 2, the necessary code can be output to the information receiver, which, for example, arrives at the same time on the display and on the input of the CPU 26.

In this mode, the signal from input 21 of the switch 17 is set to transmit the signal from the output of trigger 10. Therefore, as soon as. 1478339 _ trigger 10 will take the state of the logical unit by direct output after the comparator 3 is triggered, the voltage level of the logical unit will be formed at the input of the register 18. According to clock pulses, the bits of the register 18 in turn begin to be set in the state of a logical unit for direct outputs. In this case, as soon as the potential of the logical unit arrives at the first input of the And 12 element, the signal arriving at the CPU 26 through the switch 24 directly with one state of the signal at the input 22 or through the And 25 and the switch 24 with a different state of the signal at the input 22. The signal from input 22 controls the digital printing mode of the information receiver 4 — j printing each information on the failure of the codes or printing with sampling by the decoder 27, which is necessary when simulating special types of failures when used as 2 Receiver ADC mnogootschetnyh source codes.

After the logical unit appears at the output of the second bit of the register 18, a trailing edge of the pulse is formed on the element And 12. After some time (determined by the clock frequency of the register 18 and the number of its bits, i.e., the speed of the CPU), a similar pulse appears at the output of the element And 13, since at its third input there is a signal of a logical unit coming through the element 11 from input .21 in the considered control mode. This pulse is supplied to the start-up generator 7, as a result of which the next start-up pulse of the device appears on its first and second outputs, setting all the blocks in the initial state, except for counter 14. The process then proceeds similarly. Thus, each failure of the codes is recorded by the CPU 26 of the information receiver 4 (respectively, with a selection or not) with the automatic restart of the device.

To start at any time, the formation of the input code each time a pulse is received from the generator 7 by the shaper 5 forms a single gate arriving at the control input of the comparator 3 and prohibiting the formation of a fault signal at its output. The trailing edge of a single gate is formed at the end of the first word gate following the trigger pulse in driver 5.

Thus, each first code combination from input 19 is recorded in the memory unit 1 without comparison with the code contained in it.

To switch to the visual control mode, or continuously print current values of codes, an input of a logic unit signal is supplied to input 21, which, through the OR element 8, holds trigger 10 in the state of a logical unit by inverse output. In this case, regardless of the signals of the comparator 3, all the word strobes pass through the Ibi element at the outputs of block 2, the current values of the input code are formed. In this case, the switch 17 switches to transmitting the signal from the output of one of the bits of the counter 14. The number of this discharge is determined by the frequency of the word strobe and the speed of the CPU 26 (most often of the electromechanical type). Thus, at the output of the element And 12 periodically with the frequency of the signal change of the corresponding discharge of the counter 14, a pulse is formed that ensures the launch of the CPU 26 in the information receiver 4. In this case, a repeated (cyclic) start is excluded by a ban on the third input of the And 13 element by a signal from the bus 13 through the NOT 11 element.

Self-monitoring mode is provided by connecting the outputs 23 to the inputs 19. The communication line can be buses for parallel code transmission by the number of bits or a two-wire line with a matching device for converting the parallel code of block 15 to the corresponding serial code. After the first pulse of the start-up generator 7 (formed on all three of its outputs), the nodes are initially set up, as in the automatic code control mode. The first pulse of the start generator 7 is initiated, for example, by the operator by pressing the start button included in the start generator 7. After that, a linearly increasing code of the counter 14 begins to form upon receipt of the strobe-word from the shaper 5. In its digits, each control cycle, determined by the formation of the word strobe, generates a code one discrete larger than the previous control cycle, which passes through the block of 15 AND elements and the communication line to the inputs 19. Block 16 analyzes the input codes and, with predetermined values predetermined by the circuit design of the decoders included in this block 16, generates pulses that establish certain levels of logs through block 15 potentials in bits of the control code. The indicated codes are calculated in advance and differ from the previous ones by the amount of the comparison tolerance specified by the comparator 3 (in the simplest case, these can be potentials of logical zero in all digits). Upon receipt of the malfunction control code on the comparator 3, the latter generates the corresponding pulse and the CPU 26 prints the malfunctioning code, as described in the section on automatic comparison of code control (in this case, the potential at input 21 must correspond to the automatic code control mode). The restart pulse from the output of the And 13 element initiates the formation of a secondary pulse of the start generator 7, which sets the triggers 9 and 10 to the initial state through the OR element 8. Counter code 14 continues to increase. Further, the process continues.

Thus, on the tape of the CPU 26, a printout of predefined codes corresponding to various types of malfunctions, determined by the circuit construction of block 16, is performed. By checking the printed codes with the given ones, it is easy to establish the health of the device. When setting the display mode and printing the current values of the codes at input 21 in the self-monitoring mode of the CPU 26 of the information receiver 4 · it prints the current codes from block 15 regardless of the signals of the comparator 3. At the same time, by setting the potential at input 22, it is easy to check the operation of the decoder 27, which is used for: selection of excluded codes from the printing of the CPU 26 by comparing printouts in different modes.

Thus, the functionality of the device is expanded due to the provision of repeated repeated start-up of the device with printing of all fault codes, printing of codes with a sample providing a simple self-control mode.

Claims (2)

Claim 1. A device for monitoring a monotonously changing code by ed. St. No. 1304174, characterized in that, in order to expand the functionality by providing self-monitoring and re-starting modes, a counter, a block of AND elements, a decryption unit, a shift register, a switch, a second and third AND element and an NOT element are input into it which is combined with the control input of the commutator, mutator and connected to the second control input of the device, the third output of the start generator is connected to the input of the counter installation, the counting input of which is connected to the first output of the pulse shaper, the output The counter is connected to the first inputs of the AND block and the inputs of the decryption block, the outputs of which are connected to the corresponding second inputs of the AND block, the outputs of which are the control outputs of the device, the direct output of the second trigger is connected to the first information input of the switch, the second information input of which is connected to one from the outputs of the counter, the output of the switch is connected to the input of the shift register, the first and second outputs of which are connected to the same inputs of the second element And, the output of which is for prison to the first control input of the data receiver, a second control input of which the third control input of unit, third and fourth outputs of the shift register and the output of the element is not connected to the first - third input of the third AND gate, whose output is connected to the trigger input of the generator. 2. Device pop. 1, characterized in that the information receiver is made on the switch, the element And, the decoder and digital printing unit, the information inputs of which are combined with the inputs of the decoder and are the information inputs of the receiver, the decoder output is connected to the first input of the element And, the output of which is connected with the first information input of the switch, the second information input of which is combined with the second input of the element And it is the first control input of the receiver, the control input of the switch is the second control input of the receiver, the output of the switch is connected to the control input of the digital printing unit.