SU1478325A1 - Counter with digital display - Google Patents

Abstract

The invention relates to a pulse technique and can be used in measuring devices. The purpose of the invention is to increase reliability. The counter contains four triggers, a decoder and an indicator. The goal is achieved by executing each trigger as an RS trigger and choosing a sequence of trigger states such that the total number of elements required to implement the counter is less than in the prototype device. One of the states of the counter corresponds to turning off the indicator. 2 Il.

Description

The invention relates to a pulse technique and can be used in digital measuring devices with a visual indication of measurement results.

The aim of the invention is to improve the reliability of a pulse counter with digital indication by simplifying it.

FIG. 1 is a diagram of a pulse counter with digital indication; in fig. 2 is a decoder circuit,

The pulse counter with digital indication contains four triggers 1-4, decoder b, the outputs of which are connected to the inputs of the digital indicator 6, eleven elements AND-NOT 7-16, and the counting trigger 17, the input 18 of the initial installation, the clock input of the counting trigger is connected to the clock input 19 of the device, and a direct output connected to the first inputs of the first 7, second 8, third 9, fourth 10 and

the tenth of the 16 elements IS-NOT, and its inverse output is connected to the first inputs of the fifth 11, sixth 12, seventh 13, eighth 14, ninth 15 and eleventh 20 elements AND-NOT, the inverse output of the first trigger 1 is connected to the second inputs of the sixth 12, the seventh 13 and the tenth 16 of the NAND elements, the direct output of the first trigger 1 is connected to the second inputs of the fourth 10, the fifth 11, the eighth 14 and the eleventh 20 elements of the NAND, the inverse output of the second trigger 2 is connected to the third inputs of the eighth 14 and eleventh 20 PI-HE elements, direct output of the second trigger 2 inen with the second input of the ninth element AND-NOT 15, the inverse output of the third trigger 3 is connected to the second input of the third element AND-HE 9 and the third inputs of the fourth 10 and the tenth 16 AND-NOT elements, the direct output of the third trigger 3 is connected to the second LoginSB

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first and second 8 elements I-CHE, the inverse output of the fourth trigger 4 is connected to the third inputs of the first 7, third 9, sixth 12 AND-NOT elements and the fourth input of the eighth 14 IS-NOT element, the direct output of the fourth trigger 4 is connected to the third inputs of the second 3, p 11, the seventh 13 AND-NOT elements and the fourth entrances of the fourth 10 and eleventh 20 AND-NOT elements, and the outputs of the second 8, the fourth 10, seventh 13 eighths 14 and ten of the 16 AND-NOT elements connected respectively to the S-inputs of four triggers 1-4, the R-inputs of which are connected respectively with the outputs of the first 7, third 9, fifth 11, sixth 12 and nine 15 elements AND-NOT, the outputs of all elements AND-NOT, except for the fifth and eleventh, as well as the direct output of the second trigger 2 are connected to the inputs of the decoder 5 , the initial state setting input 18 is connected to the installation inputs of the four flip-flops 1-4 and the counting flip-flop 17 in a single state. The output of the eleventh AND-NOT element is the transfer output of the device. The first input of the decoder 5 is connected to the input of the first element AND-NOT 21 of the decoder, the second input of the decoder 5 is connected to the input of the second element AND-NOT 22 of the decoder and the second input of the third element AND-NOT 23 of the decoder, the third input of the decoder 5 is connected to the second input of the fourth element AND-NOT 24 decoder, the fourth input of the decoder 5 is connected to the third input of the fourth element AND-NOT 24 of the decoder and the second input of the fifth element AND-NOT 25 of the decoder, the first input of which is connected to the output of the fourth element AND-NOT 24 of the decoder and the input pole I-NE 26 of the decoder, the fifth input of the decoder 5 is connected to the fourth input of the fourth AND-NO 24 decoder and the second and first inputs of the seventh 27 and eighth, respectively, 28 AND-NOT elements of the decoder, the sixth input of the decoder 5 is connected to the second the inputs of the 29th, the tenth of the 30th and the eleventh 31 elements AND-NOT of the decoder, the seventh input of the decoder 5 is connected to the third input of the ninth element AND-NOT 29 of the decoder, the eighth input of the decoder 5 is connected to the first input of the tenth 30 and the second input twelfth 32 ele

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copiers AND-NOT decoder, the ninth input of the decoder 5 is connected to the first input of the thirteenth element AND-NOT 33 of the decoder, the tenth input of the decoder 5 is connected to the third inputs of the tenth 30 and thirteenth 33 elements of the AND-NOT decoder, the output of the first element AND-NOT 21 of the decoder is connected to the second input of the fourteenth 34 and the first input of the third 23 AND-NOT decoder elements, the output of the second P-NO element 22 of the decoder is connected to the first input of the fourteenth element AND-NOT 34 decoder, the output of which is connected to the fourth input of the tenth element And- NOT 30 decoder, the output of the third element AND-NOT 23 of the decoder is connected to the first input of the fourth 24, the second input of the thirteenth 33 and the first input of the eleventh 31 elements AND-NOT of the decoder, the output of the sixth element AND-NOT 26 of the decoder is connected to the first inputs of the ninth 29 and the twelfth 32 elements AND-NOT decoder, the output of the ninth element AND-NOT 29 of the decoder is connected to the first input of the seventh element AND-NOT 27 of the decoder, the output of the twelfth element AND-NOT 32 of the decoder is connected to the second input of the eighth element AND-NOT 28 of the decoder, outputs trine 33 and the eleventh 31 elements AND-NOT decoder are connected respectively with the inputs of the fifteenth 35 and sixteenth 36 elements of the AND-NOT decoder, the outputs of the fifth 25, sixth 26, seventh 27, eighth 28, ten, 30, fifth of the 35 and sixteenth 36 elements and NOT connected to the outputs of the decoder 5.

The pulse counter with digital display works as follows.

In the initial state, a logical zero signal arrives at the input of the installation of the single state 18, as a result of which four triggers 1-4 and the counting trigger 17 are set to one, and the logical zero signal is present only at the output of the second element IS-NE 8. This Pulse counter code combination 11111 is prohibition for decoder 5, and digital indicators are extinguished.

With the arrival of the first pulse on the clock bus, the 19th counting trigger 17 is set to the hoop state, as the outputs of only the fifth 11th and the ninth

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15 NAND elements are present in terms of nullity state of the first 1

and the third 3 flip-flops and saving the logical zero signal at the output of the tenth NAND element (6. The seventh pulse on the clock bus 19 sets the counting trigger 17 to the zero state, the output of only the seventh AND-NE element 13 is a signal of 10 logical zero, which leads to a change in the code combination of the four flip-flops 1-4 from 0001 to 0011 and the preservation of the logical zero signal at the output of the seventh element IS-NOT 13. 15. The eighth pulse on the clock bus 19 sets the counting trigger 17 to one, at the output of only the second element and- NOT 8 there is a logical zero signal that the coercion of a logical zero signal on a 2O AIT to the installation of the first trigger 1 during the third element IS-NOT 9. From one state, unchanged by the third pulse on the clock of the previous states of the second 2, in the case of 19, the counting trigger 17 of setting 3 and the fourth 4 triggers is in the zero state, the output of the logical zero signal is stored only at the eighth element AND-NOT 14 at the 25th output of the second element and -NE 8. logical zero signal

logical zero, which leads to the installation of the third 3 and fourth 4 triggers in the zero state, to the immutability of the single states of the first 1 and second 2 triggers and the preservation of the logic zero signal at the output of the ninth AND-NOT element 15. With the arrival of the second pulse on clock bus 19 counting trigger 17 is set to one state, at the output of only the third element IS-HE 9 there is a logical zero signal, which leads to setting the second trigger 2 to the zero state, unchanged zero states of the third 3 and four That 4 and single state of the first 1 flip-flops, as well as a saved pulse on the clock bus 19 sets the counting trigger 17 to the zero state, at the output of only the fifth AND 11 element there is a logical zero signal, which leads to a change in the code combination flip-flops 1-4 from 1011 to 1001 and saving the logical zero signal at the output of the fifth IS 11 element.

which leads to the installation of the third trigger 3 in a single state, to the immutability of the states of the first 1, second 2, fourth 4 triggers and the preservation of the logical zero signal at the output of the eighth AND-NOT element 14. With the arrival of the fourth pulse on the clock bus 19, the counting trigger 17 is set to one, at the output of only the first element of NAND 7 there is a logical zero signal, which causes the combination of triggers 1-4 0010 to be set and the signal of the logical zero at the output of the first element NAND 7. Fifth pulse n and the clock bus 19 sets the counting trigger 17 to the zero state, at the output of only the sixth element AND-NO 12 there is a logical zero signal, which leads to a change in the code pattern of the triggers 1-4 from 0010 to 0000 and the preservation of the logical zero signal at the output of the sixth element IS-NOT 12. With the arrival of the sixth pulse on the clock bus 19, the counting trigger 17 is set to one, the output of only the third 9 and tenth 16 IS-NOT signals a logical zero, which causes the second trigger 2 to be set to zero with the fourth flip-flop 4 is in the single state, to the third 3 flip-flop and the preservation of the signal of the logical zero at the output of the tenth AND – NO element (6. The seventh pulse on the clock bus 19 sets the counting trigger 17 to the zero state, at the output of the seventh IS-NOT 13 element only there is a signal 0 logical zero, which changes the code combination of four triggers 1-4 from 0001 to 0011 and preserves the signal of the logical zero the output of the seventh element IS-NOT 13. 5. The eighth pulse on the clock bus 19 sets the counting trigger 17 to one, the output of only the second element IS-NE 8 has a logical zero signal, which causes the AIT to install the first trigger 1 in one state, the immutability of the previous states of the second 2, third 3 and fourth 4 triggers and the preservation of the signal of logical zero 5 and the output of the second element and -NONE 8.

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The ninth pulse on the clock bus 19 sets the counting trigger 17 to the zero state, at the output of only the fifth AND 11 element 11 there is a logical zero signal, which changes the code pattern of the triggers 1-4 from 1011 to 1001 and preserves the logical zero signal at the output of the fifth element AND-NOT 11.

With the arrival of the tenth pulse of the counting clock on the clock bus, the 19 counting trigger 17 is set to one, the output of only the fourth AND-NOT element 10 is a logical zero signal, which changes the code pattern of the triggers 1-4 from 1001 to 1101 and saves the signal logical zero at the output of the fourth element AND-NOT 10. The eleventh pulse clock 19 in clock sets the counting trigger 17 to the zero state, the output of only the fifth 11, ninth and 15 elements AND-NOT contains logical zero signals, which leads to ovke third 3 and fourth 4 flip-flops in the null state and the previous conditions immutability flops 1 and 2. In this case, only the output of the ninth AND-NO element 15 is present a logic zero signal confirming the null state of the fourth flip-flop 4.

The code combination of the counting trigger 17 and the triggers 1-4 with the arrival

The eleventh counting pulse coincides with the code combination of counting trigger 17 and triggers 1-4, resulting from the arrival of one counting pulse. Further, with the arrival of counting pulses, the code patterns of the pulse counter are repeated, with the code patterns 11101, 01100; 11000,01010, 10010, 00000, 10001, 00011, 11011, 01001 correspond to the significant digits from 0 to 9, and the code combination 11111 - to insignificant zeroes in the count that are to be quenched (zero on the digital indicator 6 is canceled until the signal appears on the clock bus 19, which can be connected to the transfer bus of the previous decade of the pulse counter). The elements AND-NO 21-36 convert the code at the outputs of the elements of the IS-NOT counter and the output of the second trigger 2 into a seven-segment code.

Claims (1)

Invention Formula A pulse counter with digital indication, containing four flip-flops, a clock input, a setup input of the initial state, a decoder whose outputs are connected to the corresponding inputs of a digital indicator, the decoder contains eleven NAND elements, characterized in that simplify, the triggers are in the form of RS-triggers, eleven NAND elements and a counting trigger, the clock input of which is connected to the clock input of the device, are entered into the counter, the forward output is connected to the first the inputs of the first, second, third, fourth and tenth elements are NAND, and the inverse output is connected to the first inputs of the fifth, sixth, seventh, eighth, ninth and eleventh elements of NAND, the inverse output of the first trigger is connected to the second inputs of the sixth the seventh and tenth elements of NAND, the direct output of the first trigger is connected to the second inputs of the fourth, fifth, eighth and eleventh elements of NAND, the inverse output of the second trigger is connected to the third inputs of the 8th and 11th elements of NAND, direct output the second a trigger coupled to a second input of the ninth element 0 five 0 five 0 five 0 five 0 five the NID, the inverse output of the third trigger is connected to the second input of the third NAND element and the third inputs of the fourth and tenth NAND elements, the direct output of the third trigger is connected to the second inputs of the first and second NAND elements, the inverse output of the fourth the trigger is connected to the third inputs of the first, third, sixth NAND elements and the fourth input of the eighth NAND element, the direct output of the fourth trigger is connected to the third inputs of the second, fifth, seventh AND-NOT elements and the fourth inputs of the fourth and eleventh The NAND elements and the outputs of the second, fourth, seventh and eighth, tenth elements of the NAND are connected respectively to the inputs of the first, second, third and fourth flip-flops, the R-inputs of which are connected respectively to the outputs of the first, third, fifth and sixth , the ninth element, NAND, the outputs of the second NAND element and the direct output of the second trigger are connected respectively to the first and second emanations of the decoder, the outputs of the ninth, seventh, first, third, eighth, fourth, sixth, tenth elements AND -Not connected accordingly to the third, fourth, fifth, sixth, seventh, eighth, ninth and ten inputs of the decoder, the output of the eleventh element IS-NOT is connected to the transfer output, and the installation input of the initial state of the device is connected to the installation inputs of 1 all triggers, and five AND-NOT elements are entered into the decoder, the first input of the decoder is connected to the input of the first AND-NOT element of the decoder, the second input of the decoder is connected to the input of the second AND-NOT element of the decoder and the second input of the third AND-NOT decoder, the third input of the decoder It is united with the second input of the fourth AND-NOT decoder element, the fourth input of the decoder is connected to the third input of the fourth AND-NOT decoder element and the second input of the decoder's AND-N element, the first input of which is connected to the output of the fourth AND-AND decoder element and the sixth input element AND-NOT decoder, the fifth input of the decoder is connected to the fourth input of the fourth element AND-NOT decoder and the second and first inputs of the seventh and eighth, respectively, AND-PE decoder, the sixth input of the decoder is connected to the second by the inputs of the ninth, tenth, and eleventh elements of the AND-NOT decoder, the seventh input of the decoder is connected to the third input of the ninth element AND-NOT of the decoder, the eighth input of the decoder is connected to the first input of the tenth and the second input of the twelfth elements AND-NOT decoder, vir the first input of the decoder is connected to the first input of the thirteenth element AND-NOT of the decoder, the tenth input of the decoder is connected to the third inputs of the tenth and thirteenth elements AND-NOT of the decoder, the output of the first AND-NOT decoder is connected to the second input m of the fourteenth and the first input of the third element AND-NOT decoder, the output of the second element AND-NOT decoder is connected to the first input of the fourteenth element AND-NOT decoder, the output of which is connected to the fourth input ten 7832510 the tenth element AND-NOT decoder, the output of the third element N-NOT decoder is connected to the first input of the fourth, the second input of the thirteenth and the first input of the eleventh elements AND-NOT decoder, the output of the sixth element AND-NOT decoder connected to the first inputs of the ninth and twelfth elements decoder, the output of the ninth element AND-NOT decoder is connected to the first input of the seventh element AND-NOT decoder, the output of the twelfth element AND-NOT decoder is connected to the second input of the eighth element AND-NOT decoder, the outputs are triad The ninth and eleventh elements of the AND-NOT decoder are connected respectively to the inputs of the fifteenth and sixteenth elements of the AND-NOT decoder, the outputs of the fifth, sixth, seventh, eighth, tenth, fifth and sixteenth elements of the AND-NOT decoder are the corresponding outputs of the decoder 25 flats. 15 20 Shig1