SU1474631A1 - Data input unit - Google Patents

Abstract

The invention relates to the field of automation and computer technology and allows to increase the reliability of the input information. The device contains a pulse generator 1, a decoder 2, the first, second and third counters 3,4 and 5, multiplexer 6, register 7, a block of switching elements 8, the first and second elements are HE 9,10, the first, second and third triggers 11,12 and 13 and element And 14. As part of the device there are no traditional elements of delay as a means of protection against chatter. 1 il.

Description

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The invention relates to computing and can be used in data entry devices.

The purpose of the invention is to increase the reliability of the input information,

 The drawing shows the functional diagram of the device.

The device for entering information contains a generator 1 pulses decoder 2 5 first 3, second 4 and third 5 counters, multiplexer 6, register 7, block 8 of switching elements, first 9 and second 10 elements NOT, first 11 9 second 12 and third 13 triggers and element and 14.

The device works as follows.

In the initial state (the keys are not pressed), the generator of 1 pulses, the first 3 and second 4 counters, work. With each pulse of overflow of the counter 4, the counter 3 increases its state by 1. The overflow signal (output P) of the counter 3 establishes the initial zero states of the flip-flops 11 and 13. The flip-flop 12 is reset by a signal from the information receiving device.

When you press the key of the block 8, the contact resistance changes with. by bounce and at the output of multiplexer 6 a signal is formed in the form of a burst of pulses. The number of pulses in a burst depends on bounce, but a single pulse for cp & trigger 11 is enough. The maximum number of pulses in a burst is determined by the digit size of counter 4 and is practically equal to 8-16. Important is the equal size of the second and third counters 4 and 5.

When two or more keys of block 8 are simultaneously pressed, the number of bursts of pulses exceeds the maximum number of counter 5 and the overflow signal of the third counter 5 resets the first counter 3. Each time the keys are pressed, the counting starts again and before the counter 2 overflow does not reach, the trigger 13 remains the same (zero) state and trigger 32 is not set.

If one key of block 8 is pressed, then the overflow signal of the first counter 3 first sets the trigger 13, and then the trigger 12. By the signal of the readiness trigger 12, the information receiving device reads the code,

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fixed in register 8 through element 14 by trigger 13. After reading, the response signal clears trigger 12. By holding the keys each time during the counting period, trigger 11 is set and the trigger state 13 is confirmed, Since trigger state 13 does not change, trigger 12 is zero state.

When the keys are released, the trigger 11 is not installed and the trigger 13 is reset — the circuit occupies the initial state.

The gating of the decoder 2 by the sigal of the clock generator 1 makes it possible to issue a signal from the decoder 2 during the transition of the first counter 3 from one state to another, i.e. when its state at the input of the decoder 2 is undefined. This circumstance provides a strictly sequential interrogation of keys and misses: there are possible situations of code distortion when pressing several keys simultaneously.

As part of the device, there are no traditional delay elements as a means of protection against chatter. The proposed connections to the device elements allow the use of keys with practically any cracking time and ensure reliable operation of the device.

Claims (1)

Invention Formula Information input device containing a pulse generator, first counter, decoder, multiplexer, switching element block, first and second triggers, AND element, registers first KE5 element of the decoder are connected to the inputs of the hybrid element communi- cation unit, the outputs are connected to the information inputs the multiplexer, the outputs of the first counter are connected to the information inputs of the decoder, the address inputs of the multiplexer and the information inputs of the register, the outputs of which are information outputs and the device of the second flip-flop output is strobirugoschim output device reset input - Device reset input, first latch output is connected to the D-input of the second flip-flop, a clock input of the first flip-flop soedi314746314 Yen with the overflow output of the first counter, the counting input of which is co-counter, and the D input with a bus zero-dinin with the output of the multiplexer, the device’s BHO potential, the clock of setting the first trigger and the register chevhod connected to the output of the Element-Rez first element NOT with And, the house of the element And, the second entrance of which By the fact that, in order to increase reliability, it is connected to the inverse output of the thirdness of the input information, in a non-trigger, the D input of which the second and third counters are connected, the output of the first trigger, the third trigger and the second element NOT, the third input of the third trigger through the output the pulse generator is connected to the P ° element is NOT connected to the output with the counting input of the second overflow counter of the first counter, lr and the gate input of the decoder, my output of the third trigger is connected overflow output of the second counter with a clock input of the second trigger, connected to the counting input of the first 15 output of the first counter overflow counter, the reset input of which is connected-connected to the reset input of the third with third party overflow output.