SU1450099A1 - Pulse duration selector - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and remote control devices. The pulse train selector contains the generator 1, counters 2-4 pulses, elements AND 5-8, shapers 9 and 10 pulses, element NOT 11, code buses 12-14, input bus 15, output bus 16. Setting the duration code to the maximum allowed the pauses between the pulses of the series, as well as the duration and zone of tolerances of the duration of the selected pulses, allow for the possibility of operative reorganization of the specified parameters and equal accuracy of pulse selection in a wide range of durations. 2 Il.

Description

The invention relates to a pulse

Technique and can be used in automation and telemechanics devices.

The purpose of the invention is the provision of 5 opportunities for selection of a series of pulses of duration yo.

Pa figure 1 shows the structural electrical circuit of the device; Fig. 2 time diagrams explaining his ’θ work.

The selector (figure 1) contains a generator 1, from first to third counters

2-4 pulses, the subtraction inputs of which are connected to the outputs from the first to the third elements And 5-7, the output of the loan counter 4 is connected to the first input of the fourth element And 8, and the loan outputs of the meters 2 and 3 are connected to the inputs respectively 20 Foam of the first and the second shapers 9 and 10 pulses. The output of the shaper 9 through the element HE 11 is connected to the second input of the element And 8. The information inputs of the counters 2-4 are connected respectively with the first through third code buses 12A14. The nitrous oxide input of counter 2 is connected to the input Bus 15, and the output of the And 8 element is connected to the output bus 16. The first inputs of the Element 30 and 5-7 are connected to the output of the generator 1, and the second inputs are connected to the loan outputs of the 2j-4 counters, respectively . The recording entries of the counters 3 and 4 are connected * respectively with the output 35 of the loan counter 2 and the output of the shaper 10.

The selector works as follows.

The generator 1 generates pulses 40 with a period b ₀ (figa), the choice of £ ₀ is determined from the requirements for the accuracy of the device. In the initial state, i.e. if there are no pulses of the input signal on bus 15, and therefore 45 and the recording input of counter 2, there is a logic unit signal that allows counter 2 to work in counter mode, therefore counter 2 is in the zero state and gg is a logic zero signal at its output, or if the state counter 2 is nonzero, then the signal of a logical unit at its output, entering the second input of AND element 5, opens it, allowing $$ pulses from generator 1 to the subtraction input of counter 2 until counter 2 is set to zero from the state and the logical zero signal from its output, arriving at the second input of the And 5 element, closes the latter, in addition, this logical zero signal, coming to the recording input of counter 3, sets the latter to recording mode, while counter 3 will be recorded the code of the number N, since on the bus 13 there is a code of this number, and at its output a logical unit signal that goes to the input of the And 6 element opens it, allowing pulses from the generator 1 to the subtraction input of the counter 3, but the state of the counter 3 does not change since the entry is written and, like the reset input, has priority over the subtraction input.

At the output of the pulse shaper 10 in the initial state there is also no signal of a logical unit, which, coming to the input of the recording of counter 4, allows the latter to work in counting mode, therefore, counter 4 is also in the zero state and its output is a logical zero signal, since if the state of counter 4 is nonzero, then a logical 1 signal at its output, coming to the second input of AND element 7, opens the latter, allowing pulses from generator 1 to the counting input of counter 4 until counter 4 is set tsya in zero state signal and wherein the logic zero at the output of AND gate 7 closes.

The input signal in the form of series with different durations, and the number, period and duration of pulses in a series in the general case are random and in this series', can even be unstable, arrives on bus 15 and then to the input of counter 2 (Fig. 26) . The logical zero signal of the first pulse of the series sets the counter 2 to the recording mode, and the code of the number K will be written in the counter 2. Since the code of this number is present at its information inputs, and the signal of the logical unit is at its output (Fig.2c), at the end of the first pulse, the signal of the logical unit of a pause between the first and second pulses of the series, entering the input of the counter 2, allows the latter to work in the counting mode. ' If the pause duration is less than the K'vp time, which is achieved by the appropriate choice of K, then counter 2 will not have time to reset to the arrival of the second pulse, therefore, a logical unit signal will remain at its output, and the logical zero signal of the second pulse of the series will again set counter 2 to the recording mode and so on, at the end of the last pulse of the series, the signal of the logical unit between the series of pulses, arriving at the input of the recording of counter 2, allows it to work in counting mode and after a time to £ _0, counter 2 sets to zero , while at its output appears a signal of logical zero (pigv).

The signal from the output of the counter 2 is fed to the input of the shaper 9, while the shaper 9 generates a pulse '(Fig.2d), which corresponds to the trailing edge of the pulse from the counter 2, which is supplied through the element 11 to the second input of the element And 8, and its duration is set, based on the requirements of subsequent devices.

In addition, the signal of the logical unit from the counter 2, coming to the input of the recording of the counter 3, allows it to work in the counting mode, since the number 3 code is written in the counter 3, if the duration of the signal of the logical unit from the output of the counter 2 is less than the time N, counter 3 it doesn’t have time to reset to zero, while at its output there remains a signal of a logical unit and a logic zero signal, at the end of the pulse from the output of counter 2, counter 3 is again set to recording mode. If the duration of the signal of a logical unit from the counter is more than Νί ₀ , then after a time relative to the leading edge of the pulse from the output of counter 2, the counter is set to zero, and a logical zero signal appears on its output (Fig.2d), until the pulse ends from the output of the counter 2. At the end of the pulse from the output of counter 2, the logical zero signal again sets counter 3 to recording mode, in this case. a signal of a logical unit appears on its output (Fig.2d). The signal from the output of the counter 3 is fed to the input of the pulse shaper 10, which gives a pulse (Fig. 2f) corresponding to the leading edge of the pulse from the output of the counter 3, the duration of which is determined by the speed of the counter 4 by the recording input.

The logic zero signal from the output of the shaper 10, arriving at the recording input of the counter 4, sets it to the recording mode, while in the counter 4 the code of the number M will be recorded, since there is a code on its information inputs. of this number, and at their output a signal of a logical unit (Fig.2zh). At the end of the pulse of the shaper 9, the signal of the logical unit, arriving at the input of the counter 4, allows it to work in the counting mode and after a while the counter 4 is set to zero, and a logical zero signal appears at its output (Fig.2zh).

Therefore, if the pause duration between series pulses, t _p and · the pause duration between series T _p satisfy the condition t _n ^ Κΐ ₀ * Τ _π , then a pulse is generated at the output of counter 2 (Fig.2c), the leading edge of which coincides with the leading edge the first pulse of the series, and the back pulse is delayed by. time relative to the trailing edge of the last pulse of the series, i.e. whose duration is (Τ ^ + Κΐο), where T _s is the duration of this pulse (T _s + K * s _s ) <Νί ₀ or T _s ζ (Ν-Κ) ί ₀ , then the output of counter 3, and, accordingly, at the output of counter 4, the signal does not change, if the duration of a series of pulses is Τ _ο 7 (Ν-Κ) ΰ ₀ , then a pulse appears at the output of counter 3 (Fig. 2e), the leading edge of which is delayed by ремя time Νί ₀ relative to the leading edge of the first pulse of the series, this front through the pulse shaper 10 causes the counter 4 to operate, which generates a pulse (Fig.2zh), the leading edge of which coincides with the leading edge ntom pulse from the counter 3 and the duration of which is equal Μ1ί ₀ (because the pulse width shaper 10 is much smaller than C _o, it can be neglected).

Thus, since at the second input of the And 8 element, the signal of the logical unit from the output of the HE 11 element will only be in time (Το + относительноζ) relative to the leading edge of the first pulse of the series, and at the first from the output of the counter 4 only if T _with 7 ( Ν-Κ), after a time Ν <ζ, relative to the front edge of the first pulse and for a series of audio vreme5 MC _0, then the output of aND gate 8 (fig.2z) and TB respectively at the output bus signal will only tog- '| yes when they coincide in time, and this will be only if (N-K) С »Т _с <(N-K + M), i.e., when

The duration of the series is within the specified limits.

The advantage of the proposed selector is that the duration of the maximum allowable pause between the pulses of the series, as well as the duration and the zone of permissible deviations of the duration of the selected series, are set by the code, which is more convenient and provides the series with a zone.

selectivity selectivity

Claims (1)

Form 1450099 6 by the generator output, and the second inputs with the loan output, respectively, from the first to the third pulse counters, the information inputs of which form respectively the first to third code buses, the recording input of the first pulse meter being connected to the input bus, and the loan output to the recording input the second pulse counter, as well as the first pulse shaper, the element NOT, the fourth element AND and the output bus, characterized in that, in order to enable selection of a series of pulses by duration, a second pulse generator is introduced into it Pulse collector, the input of which is connected to the output of the loan of the second pulse counter, and the output - to the recording input of the third pulse counter, the loan output of which is connected to the first input of the fourth AND element, whose output is connected to the output bus, and the second input through the element NOT to the output the first pulse shaper, the input of which is connected to the loan output of the first pulse counter. wide range of inventions Selector ι --------- ------ -------------- containing first to third pulse counters, the subtraction inputs of which are connected to the outputs, respectively, from first to third And elements, the first inputs of which are connected with pulses in duration,