SU1439746A1 - Information converter - Google Patents

Abstract

The invention relates to automation and computing and could. it does. be used in the equipment for processing and recording electrical signals recorded on various types of carriers, for example, on magnetic tape. or transmitted via communication lines, when it is necessary to accurately link the events of the experiment to the time scale. The purpose of the invention is to increase the reliability of the conversion. The converter contains an optoelectronic switch 2, a delay element 3, elements 4-7, triggers 8-10, a shift register 11, a comparison circuit 12, a constant reference block 13, counters 14, 15, a clock pulse generator 16, a differentiation block 17, a NOT element 18 with related communications. The converter allows to increase the reliability of the conversion of code time sequences and to ensure accurate binding of the obtained processing results in the time scale. 1 il. § (L s

Description

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The invention relates to automation and computing technology, can be used in equipment processing and recording electrical signals, in addition, the proposed device acquires particular importance in automating the production of various characteristics of non-stationary random processes that require accurate linking of expert events to a time scale, when large parts of experimental information are forced to register in parallel with the time signals on different carriers and, for example, on a magnetic tape.

The purpose of the invention is to increase the reliability of the conversion.

The drawing shows a structural diagram of the transducer.

The converter has information input 1, optoelectronic switch 2, delay element 3, elements 4-7, triggers 8-10, shift register 11, comparison circuit 12, constant setting unit 13, counters 14 and 15, clock generator 16, differentiating unit 17, element 18, outputs 1 9 and 20.

The converter works as follows.

Input 1 is presented with a current time message in the form of a code parcel. The current time report consists of a constant part, for example, the binary number 11, and a variable part, the number of positions of which is determined by the number of bits needed to encode the entire length of time during which the data from the experiment being recorded is recorded. A sequential time code from input 1 passes through an optoelectronic switch 2, which is opened by permitting voltage from the output of the HE element 18, to the output of the optical electronic switch 2 are connected in parallel the first input of the first trigger 8 and the input of the delay element 3, the code sequence from which is fed to the first input of the first element 4, to the second input of which the resolving potential is supplied from the output of the first trigger 8.

From the output of the optoelectronic switch 2, a consecutive time code is supplied, which has, for example, for a reference point, the following form: 1100 ,,, 00 and for the first time unit is 1100

01 and so on Trigger 8, when the first unit of the constant part of the code sequence arrives at it, is reassigned, and the voltage from the output of trigger B permits passage of the received time code sequence through element 4.

The serial code from the output of the AND 4 element is in parallel supplied to the first input of the shift register 11, and the S input of the second trigger 9, which is transferred by the first pulse of the received sequence and enables the writing of the sequence to the shift register 11, simultaneously opens the third element AND 6 the first input of which is supplied with clock pulses from the generator output of 16 clock pulses. The clock pulses from the output of the meteor element I 6 are simultaneously fed to the first input of the second counter 15 and the third input of the shift register 11. In this way, the received sequential code is recorded in shift register 11. The second counter 15 counts N clock pulses, N is equal to the number of positions of the received sequence, including the constant and variable parts of the code dressing. After the second counter 15 counts N pulses, a pulse is supplied from the counter output to the R input of the second flip-flop 9 which overturns and prohibits the passage through the third element AND 6 clock pulses that were fed to the third input of the shift register 11, the voltage records from the second input of the register 11 shift. At this moment, the received current time code sequence is recorded in shift register 11. The first and second inputs of the second element 5 and the comparison circuit 12, the output of which is connected to the 3-INPUT of the third trigger 10, are connected in parallel to the outputs of the (n + 1) -th and (n + 2) -th bits of the shift register 11.

When the values recorded in the (n + I) and (n + 2) bits of the shift register coincide with the corresponding values recorded in block 13, a pulse arrives from the output of the comparison circuit 12, which is fed to the S input of the trigger 10. At the same time the first and second inputs of the second element And 5 served high potentials

from the outputs (n + 1) and (n + 2) of the bits of the shift register n, which in turn correspond to the values of the constant part of the received code sequence.

From the output of the second element And 5 to the output of the signal of validity 19, a signal is applied that undermines the fidelity of the conversion and reception of the code sequence. From the output of the third trigger 10, a signal is fed through the element HE 18 to the optoelectronic switch 2, which for it is a signal that prohibits reception, and to the differentiating unit 17 and the second input of the fourth element And 7, for which it is permissive.

The fourth element And 7 passes the clock pulses from the generator 16 to the first input of the first counter 14, which counts M pulses, after which it signals the completion of the conversion receive cycle and the storage of the time code sequence. The impulse to terminate the count from the exit of the first counter 14 is applied to the second input of the third trigger 10, which flips over and closes the fourth element AND 7, embraces the first and second counters 14 and 15, the shift register 11, etc. Accordingly, the voltage from the output of the third trigger 10 through the element NOT 18 opens the optoelectronic switch 2. The converter is ready to receive and convert a new code sequence of time. The outputs of the information converter are the outputs of the n bits of the shift register 11.

The differentiating unit is a series-connected RC chain and an inverter, the output of which is the output of the unit and its input is the input of the differentiating KS chain. Unit 13 may, for example, be made on two position switches, one position of which is connected to a voltage corresponding to logical 1, and the second position to a voltage corresponding to logical

must correspond to the number of bits of the constant part of the code sequence of time.

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An information converter containing a shift register, the first information input of which is connected to the output of the first element I, the first input of which is connected to the output of the first trigger, a clock pulse generator, characterized in that, in order to increase the reliability of the conversion, a comparison circuit is introduced into it, the second and the third triggers, the delay element, the optoelectronic key, the first and second counters, the second, third and fourth elements AND, the setpoint constant block, the differentiating unit, the element NOT whose ervym input optocoupler, a second input of which is connected to the data input of the converter, and an output connected to the input of the delay element 5 and ihodom first flip-flop 25 whose input R-and R-input of the second

the trigger is connected to the output of the second: Counter, the counting input of which is connected to the output of the third element And, the first input of which and the first input 30 of the fourth element And are connected to the OUTPUT of the clock generator, the output of the fourth element And is connected to the counting input of the first counter, the zeroing input of which and the inputs of zeroing of the second counter and shift register are connected to the output of the differential of the lean unit, whose input and inputs of the element NOT and the fourth element I are connected to the output of the third trigger, whose R and S inputs are coi Ina, respectively, with the output of the first counter and the output of the comparison circuit, the first input of which is connected to the output of the constant setting block, and the second and third inputs are combined respectively with the first and second inputs of the second And element and connected to the outputs of the (n + 1) -th and + 2) th shift register bits, the first and second shift inputs of which are connected respectively to the output of the third element And the output of the second trigger, the output connected to the second input of the third element,

 Oh, the number of switches 55 S-input of the second trigger

connected to the output of the first element And, the second input of which is connected to the output of the delay element.

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Claims (1)

An information converter containing a shift register, the first information input of which is connected to the output of the first element And, the first input of which is connected to the output of the first trigger, a clock generator, characterized in that, in order to increase the reliability of the conversion, a comparison circuit is introduced into it, the second and third triggers, delay element, optoelectronic switch, first and second counters, second, third and fourth elements AND, constant setting unit, differentiating block, element NOT, whose output is connected to the first the input of the optoelectronic switch, the second input of which is connected to the information input of the converter, and the output is connected to the input of the delay element and the S-input of the first trigger, the R-input of which and the R-input of the second trigger are connected to the output of the second counter, the counting input of which is connected to the output the third element And, 'the first input of which and the first input of the fourth element And are connected to • the output of the clock pulse generator,' the output of the fourth element And is connected to the counting input of the first counter, the zeroing input of which and the zeroing inputs I of the second counter and the shift register are connected to the output of the differentiating block, the input of which and the inputs of the element NOT and the fourth element AND are connected to the output of the third trigger, the R- and S-inputs of which are connected respectively to the output of the first counter and the output of the comparison circuit, the first input of which is connected to the output of the constant setting unit, and the second and third inputs are combined respectively with the first and second inputs of the second AND element and are connected to the outputs of the (n + 1) th and (n + 2) th bits of the shift register, the first and second shift inputs of which from respectively unified with the output of the third AND gate and the output of the second flip-flop, the output connected to the second input of the third AND element is the one, S-input of the second flip-flop connected to the output of the first AND gate, a second input connected to the output of the delay element.