SU1430986A1 - Device for displaying symbols on crt screen - Google Patents

Abstract

The invention relates to computing and automation and can be used in devices for forming symbols on a CRT screen. The purpose of the invention is to simplify the device and increase its reliability by reducing the information volume of the memory block by two bits in each vector of the generated symbol, which is achieved by introducing into the device of the converter 10 codes and the encoder 11 and the corresponding functional links. The device contains memory blocks 1 and 3, counter 2, 4 pulse generator, control unit 5, converter 6 code - time interval, register 7, sweep generator 8, backlight unit 9, code converter 10 and encoder 11. The invention allows perform a logical conversion of 8-bit character firmware codes to 10-bit c codes. their subsequent conversion to analog signals. 11 ill., 3 tab. (ABOUT

Description

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The invention relates to computing and automation and can be used to form symbols in information display devices on a CRT.

The purpose of the invention is to simplify the device and increase its reliability by reducing the information volume of the memory block by two bits in each vector of the generated symbol.

FIG. 1 shows a block diagram of the device; in fig. 2 - functional diagram of the first memory block, the counter and the second memory block; in fig. 3 -; functional diagram of the oscillator; ia fi | -. 4 - functional diagram of the .block un-ravle 11i; in fig. 5 - functional scheme of the code-time converter; |; FIG. 6 - register is functional; im fig. 7 - functional block diagram of the backlight; in fig. 8 is a functional sweep generator circuit; in fig. 9 is a functional diagram of a co-iois converter; pas figs. 10 - functional scheme 111Н (|) of the rator; pas figs. 11 is a timing diagram of the operation of the device (for symbol 9).

The device contains the first memory block 1, a counter 2, a second memory block 3, a pulse generator 4, a control block 5, a code-time interval converter 6, a register 7, a sweep generator 8, a backlight unit 9, a code converter 10, an encoder 11. Positions 12 and 13 denote the cooTiiCTCTBeHHO input “Symbol code and device sync input”, and positions 14, 15 and 16 denote outputs for connecting to the deflection path of a CRT, output for connecting to mode. 1 torus CRT and the output “End of the device siavol, respectively.

The unit 1 pa.mti consists of memory elements I7.I and 17.2, loaded on the resistor assembly 18.

Counter 2 consists of three typical 4-bit counters 19.1 -19.3.

Memory unit 3 consists of a memory element 20 loaded onto a resistor assembly 21.

The emulsifier generator 4 is made according to the generator with delayed feedback and contains a trigger 22, an HH element 23, an AND 24 element, a delay element 25.

Control unit 5 contains NOT elements 26-30, AND-NE elements 31 and 32, AND elements 33 and 34, triggers 35.1 and 35.2, and a single vibrator 36.

Converter 6 code-time interval consists of subtractive counter 37 and one-shot 38.

Register 7 consists of two D-triggers 39 and 40.

The illumination unit 9 contains a matching usi; | itel 41, delay element 42 and video amplifier 43.

Sweep generator 8 consists of two transducers 44 and 45 levels of logic signals 5V to levels 10-12 V, a diode

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46 commutating bridge, two current regulators 47 and 48, a reset key 49 and an integrating capacitor 50.

Converter 10 codes contains the elements NOT 51-54 and the elements AND NOT 55-64. His work is described in the truth table given in Table. I.

The encoder II contains the elements HE 65 and 66, the elements AND 67-71, the element NO 72, the element E 73, the element NOT 74. His work is described in the truth table in Table. 2

The memory unit 1 is designed to record and store codes of the initial addresses of the generated signals. The memory unit 3 is intended for recording and storing the firmware of character construction.

Counter 2 is intended to set an address code at the input to memory block 3.

The pulse generator 4 is designed to form a TI pulse burst within the symbol generation time.

The control unit 5 is designed to generate the following signals; SAR - recording the initial address of TI 1 - clock pulses that are different from TI by the absence of the first pulse, GATE 2 - the switching signal of the sweep generator, CS - the end of the signal.

Converter 6 code-time interval is designed to generate a signal SLE with time intervals proportional to the code of the length of the vector and the period of the pulses TI 1.

Register 7 is designed to record and store character vector codes for the operating time of the sweep generator 8, which converts the digital codes from the output of register 7 to analog functional scan voltages of the Ux and Uy symbol in accordance with the code value at its input.

The illumination unit 9 is designed to delay and amplify a one-bit code of the illumination of the sig.vol vector vectors to the amplitude necessary for modulating the CRT beam by brightness.

The code converter 10 is designed to convert a 4-bit vector sweep code into a 2-bit code of its length, as well as to generate sweep generator control signals.

The encoder II is designed to form a 3-bit code of the length of the vector for the converter 6 code-time interval.

The device works as follows.

The character code from the input 12 of the device is fed to the address input of the memory block, which will produce an n-bit code for the initial address of the character's firmware. At the device input 13, a start-stop generator of 4 pulses is triggered by a synchronization pulse, which forms a burst of TI pulses at a given frequency within the time limit.

symbol formation. These pulses go to control unit 5, which of them generates a SAR signal and a packet of TI 1 pulses. With a SAR signal, the code of the starting address is recorded in counter 2 and from its output goes to the address input of the memory unit 3.

The starting address of the symbol determines the cell in memory block 3, in which the first vector of the generated symbol is located.

The number of initial addresses recorded in memory block 1 corresponds to the number of characters generated. From this, the required volume of memory block 1 is selected.

Microprograms of symbols are placed in block 3 of memory and are made up of 8-bit numbers. An example of the placement of the firmware of several characters is given in Table. 3. In this table, bits XI-X3 define the horizontal component of the vector sweep along the X coordinate, and bits Y 1 — UZ — the vertical component along the Y coordinate. Bit Z defines the vector illumination, and bit T is the third digit of the vector length code.

According to the code of the starting address from the output of counter 2, memory block 3 outputs the 8-bit code of the first vector of the generated symbol. Four bits from this code (X 1, X 2, Y 1, Y 2), which determine the angular orientation of the vector relative to the coordinate axes X and Y, are fed to the converter 10 codes. The bits Xs and Y, 3, which set the direction of the vector relative to the start of the sweep (right, left, up, down) and the highlight code Z are sent to the information input of register 7.

The code converter 10 converts a 4-bit code (X 1, X 2, Y 1, Y 2) into a 2-bit vector length code (T 1, T 2) and generates the necessary control signals for the sweep generator 8.

The vector length code (T 1, T 2) goes to the first input of the tweeter 11, and its second input receives the bit 7 from the output of the memory block 3. In the encoder 1 1, a 3-bit code is formed corresponding to the numbers 1, 2, 3, 4 and 6. This code is fed to the converter 6 by a code-time interval, which, in accordance with the value of the incoming code, determines the temporal position of the SCR signals. From each successive SCR signal, the increment by a unit of the recorded code of the start address in counter 2 is produced. In addition, the SCR changes the vector codes in register 7.

After sampling the code of the first vector from memory block 3, pulses TI 1 are sent from the second output of control block 5 to the synchronous input of the converter 6 code-time interval. In the first pulse from this burst, the code-time converter 6 generates a CCBo signal, which is the code input signal of the first symbol vector

into its own counter (pos. 37 in Fig. 5) and register 7. The same signal is fed to the counting input of counter 2 and increases by one the code of the starting address written in it. At the same time, at the output of the memory block 3, the code of the second symbol vector is set, which does not change until the address code is changed.

The STROBE signal 2 from the output of the control unit 5 turns on the sweep generator 8, which begins to convert the digital codes from the output of the register 7 to the analog functional voltages of the sign sweep and and Uy. Depending on the QT values of the vector codes from the register 7 output, the sweep generator 8 will generate voltages of complex shape. Each symbol has its own form of output sweep voltages. From the output of the generator 8, the functional voltages of the sweep of the sign Ux and Ui) are fed to the input of the sign O1-o amplifier, which is loaded onto the deflecting cathode of a CRT (not shown in Fig. 1).

The backlight unit 9 outputs the backlight voltage Ua in accordance with the value of the Z code. In block 9 (FIG. 7), the backlight signal is delayed by the delay line 42 for a time equal to the delay of the voltages Uy 13 in the sign amplifier. The delay of the illumination signals improves the display of symbols on the CRT screen by eliminating gaps in the outline of characters at the junction of vectors. With video amplifier 43, the light signal is amplified to the required amplitude and fed to the output 15 of the device. From output 15, the signal Uz is fed to a CRT modulator (not shown in Fig. 1).

After displaying the first vector of the symbol at the output of the transform.h 6 code-time interval, the SQR signal is formed with a time interval proportional to the weight of the vector length code at the input and the pulse period; ov TI 1. Based on the formed SLE, the code of the second symbol vector from the output of memory block 3 and converter 10 is entered into register 7, and the code from the output of encoder 11 is entered into counter 37. With the same signal, the code of the starting address in counter 2 is increased by one more unit and the output of memory block 3 sets the code of the next third vector to form direct character.

In the further process of sampling vector codes from memory block 3 and converting them into analog functional voltages, the sweep of the symbols Yx, Uy and the illumination signals Uz are repeated.

When forming the last symbol vector from the output of the memory block 3, the zero code in all bits is received. An output 3 of the encoder 11 also generates a 3-bit zero code. which enters the reset shaper (elements NOT 27-29, element And 34 and the one-shot 36 in Fig. 5).

With this code and the last SCR, the reset driver generates a signal for the end of the symbol (CS), which brings the device to the zero state and enters the output 16 of the device to call the code of the next character from the external control device (not shown in Fig. I). The single-oscillator 36 generates a signal of a predetermined duration, which is necessary for the operation of an external control device in accordance with its interface.

In the proposed device, the firmware of the symbols is made up of 8-bit numbers, which saves two bits in each vector of the character being formed and saves the information storage space and allows the use of commercially available memory blocks with an 8-bit output, which , device

Claims (1)

Invention Formula A device for displaying symbols on the screen of a cathode ray tube (CRT), contains a first memory block whose address input is the device character code and the output is connected to the information input of the counter whose output is connected to the address input of the second block memory, pulse generator, the start input of which is the synchronous input of the device, and its output is connected to the clock input of the control unit, the first output of which is connected to the synchronous input of the code-time interval, the output of which ene to the control input 0 0 5 o the register record, the first output of which is connected to the information input of the sweep generator, the second register output is connected to the input of the backlight unit, the output of which is the output of the device for connection to the CRT modulator, the second output of the control unit is connected to the counter recording control input, the counting input of which is connected with the output of the converter the code-time interval connected to the control input of the control unit, the third output of which is connected to the control input of the sweep generator, the outputs of which are The device’s outputs are connected to the deviating tract of a CRT, the fourth output of the control unit is connected to the reset inputs of the pulse generator and the code-time interval converter, and is the output signal of the device symbol, the first output of the second memory unit is connected to the first information input of the register, characterized in that, in order to simplify the device and increase its reliability by reducing the information volume of the memory block, it contains a code converter and an encoder, the output of which is connected to and The information inputs of the code-time converter and the control unit, the information input of the code converter and the first information input of the encoder are connected to the second output of the second memory block, the second information input of the encoder is connected to the first output of the code converter, the second output of which is connected to the second information input of the register. Table 1 Continuation of table 1 table 2 1430986 10 Table 3 From s zna From P Hard currency (para. 2 r I / t Tg 434 Sincre 22 Cfnpod f FIG. five tf / 77 // (pus. u l / from 2S M 52 3HA L-. AH K5, i6 one- igb ipue 7 fie. eight one/)(( Srig. fO