JPS6230297A - Dot display signal generation circuit for dot type waveform display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to dot display data of a waveform processing device that samples an input waveform, performs linear interpolation, and then performs multi-step luminance interpolation and stores the resulting data in a RAM. The present invention relates to a dot display signal generation circuit attached to a dot type waveform display device such as a cathode ray tube display device or a recorder for converting a dot signal into an analog dot display signal.

[Prior art and problems to be solved by the invention] In dot-type waveform display devices, dot display data is usually stored in a dot pattern in a RAM with a capacity corresponding to the time axis address x amplitude address on the display screen. A dot display signal is generated by reading and scanning all amplitude addresses for each time axis address from a waveform processing device. Therefore, the capacity of the RAM naturally becomes large, and when luminance interpolation is performed, the capacity doubles by the number of bits necessary to provide luminance information for each dot data.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a dot display signal generation circuit of the type mentioned at the beginning, which can reduce the storage capacity of a RAM for storing dot display signals in a waveform processing device.

[Means and operations for solving the problems] In order to achieve this object, the present invention has constructed a dot display signal generation circuit for a dot type waveform display device as shown in FIG. The waveform processing device receives only a top address and a bottom address for each time-axis address on the display surface, as well as multi-bit luminance interpolation data for performing luminance interpolation in the direction of the amplitude address based on both of these addresses. Circuit part 1 of each bit
~4 generates a serial logic signal that uses the bottom side brightness interpolation data as brightness information in the amplitude address direction, and - the actual circuit portions 1a to 4a generate a serial logical signal that uses the top side brightness interpolation data as brightness information. Therefore, the gate circuit 5 generates a dot display signal that is linearly and brightly interpolated between the bottom and top addresses. These gate outputs are sent to the D/A converter 6 along with other bits.
When converted into an analog signal as a parallel digital input, a luminance signal of 3 stages, that is, 2 bits or more can be obtained.

For example, as shown in Figure 3(a), there are four levels (・) on the display screen.
, ■, and O) whose brightness is interpolated and displayed. In the RAM of the waveform processing device,
For example, for the time axis address N, the bottom address n and peak address n+4, which are the standards for brightness interpolation, are stored respectively, and the bottom address side brightness interpolation data (0, *, ·) in the increasing direction of the amplitude address are stored as shown in FIG. b
), the brightness interpolation data on the top address side is set to 2 bits (01, 10, 11).
01).

When displaying the address N, data (101) of the ba digit of the bottom address side luminance interpolation data is sent to the latch circuit 4 of the circuit section for the be digit shown in FIG.
a contains bo digits (
+01) is latched. When the clock count value reaches the bottom address n, the bottom address comparator 2 outputs an output and the bottom address shift register 3 starts to advance, and as shown in FIG. 3(C). As shown, the preset value is first output for three addresses, and then "1" is output.

On the other hand, the top address shift register 3a outputs "1" until the counted value reaches the peak address n+4, at which point it outputs the preset value, and thereafter outputs "O". ′ is output. Therefore, the gate circuit 5 outputs 5-digit linear/luminance interpolated data (FIG. 3(e)).

Similarly, the latch circuit 4.4a of the circuit section for 51 digits has the bottom address and top address side of b+ digit.
: The luminance interpolation data (011) and (110) are latched, and the gate circuit 5 outputs b+ digit linear/luminance interpolation data (Fig. 3(f)), and the D/A converter 6 outputs the linear/luminance interpolation data (Fig. 3(f)). Corresponding to a), a dot display signal whose level changes in four stages is output (Fig. 3 (g)
).

[Embodiments of the invention]

In FIG. 2, reference numeral 10 denotes a waveform processing device that creates dot display data that has been subjected to linear interpolation as shown in FIG. That is, as described above, the RAM stores high-intensity signals (11) for each time axis address as shown in FIG.
) Medium brightness O is (10), low brightness O is (Ol), no brightness is (00), parallel 2-bit ba, b- brightness interpolation data per address, display position of these interpolated data and linear interpolated data Four types of data are stored: a top address and a bottom address, which serve as a reference.

Reference numeral 20 denotes a dot display signal generation circuit according to the present invention attached to the cathode ray tube display device 30, which converts dot display data read out from the waveform processing device 10 to generate an analog dot display signal. This circuit has a signal processing section 20 a having the same configuration for the first bit bo and the second bit bt.
, 20b, and a D/A converter 26 that converts these 2-bit output signals into analog.

an address counter 27 that counts clocks and is cleared for each vertical rask scan of the cathode ray tube display 30;
and a clock generator 28 that generates this clock. Each signal processing unit 20a, 2
0b corresponds to the bottom at □! latch circuit 21 for address and top address
5,y al”l w,2+a l,=tE h
i, 7)'v,z(Il#IJ!Eml'o'
l ' data latch circuit 24 and top address side brightness □ degree interpolation data latch circuit 24a
, a comparator 22 that generates an output signal when the clock count reaches the latched bottom address, a comparator 22a that generates an output signal when the clock count reaches the latched top address, and the bottom side of the latch circuit 24. A shift register 23 is preset with luminance interpolation data and starts clocked stepping operation with the output signal of the comparator 22, and a shift register 23 is preset with the top side luminance interpolation data of the latch circuit 24a and starts clocked with the output signal of the comparator 22a. It is composed of a shift register 23a that starts a stepping operation, and an AND gate 27 that performs an AND operation on the output signals of both shift registers 23 and 23a.

The cathode ray tube display device 30 sequentially displays the output signals of the D/A converter 26, which are outputted in synchronization with the counting operation of the address counter 27 and the clock of the clock generator 28, on its display surface by vertical rask scanning. Note that the output of the shift register 23a is normally at H level, and the output of the comparator 23a is normally at H level.
5a starts sending out the Glycerate value.

The operation will be explained with reference to FIG.

When displaying waveforms, use a waveform processing device! Starting from 0, the top address, bottom address, and luminance interpolation data for each of the time axis addresses...N are sequentially sent to the dot display signal generation circuit 20. For example, as shown in FIG.
), the bottom address n is sent to the latch circuit 21 of both signal processing units 20a and 20b, and the top address n is sent to the latch circuit 21a of both signal processing units 20a and 20b.
+4 is latched. On the other hand, the latch circuits 24 and 24a of the signal processing unit 20a are provided with an interpolated value (101) on the bottom address side of the ba digit and an interpolated value (101) on the top address side.
), and the latch circuits 24 and 2 of the signal processing section 20b.
4a is the interpolated value on the bottom address side of b1 digit (011)
and the interpolated value (110) on the top address side are each latched.

The address counter 27 starts counting clocks, and when the counted value reaches the bottom address n, the shift register 22 starts an increment operation, as shown in FIGS. 3(C) to 3(g) described above.
The D/A converter 26 outputs a dot pulse signal (FIG. 3(g)) whose level changes in four stages for brightness modulation, and the CRT display device 3
0 displays dots with a brightness corresponding to that level.

Regarding the next time axis address N+1, the bottom address n+4 and top address n+7 are sent to the dot display signal generation circuit 20. In this case, the bottom address side luminance interpolation data sent out is the same as that of time axis address N, and the top address side luminance interpolation data is (11,00
, 00). Therefore, the output of the bo-digit AND gate is shown in FIG. 3 (h'), and the output of the b-1-digit AND gate 25 is as shown in FIG. The output is ・Figure 3 (j)
become.

For the time axis address N+4 where the top address and bottom address match, n is sent to both the top address and the bottom address, and the bottom address side luminance interpolation data (11,00,00) and the top address side luminance interpolation data (11,00,00) are sent. 00,00). Therefore, the output of the shift register 23 for both folding b+ and bI is as shown in FIG. 3(k), and the output of the shift register 23a is as shown in FIG. 3(k).
1) The outputs of the AND gater 25 of 8 digits and b are both shown in Figure 3 (intestine).

The output of 26 is as shown in FIG. 3(n). In this way, the cathode ray tube display section 30 displays the dots with luminance along the time axis from the waveform processing device IO, and displays the waveform as shown in FIG. 3(a). conduct.

In the above-described embodiment, if the scanning direction of the amplitude address is reversed, the relationship between the top and bottom is reversed. Depending on the circuit configuration, various modifications may be made within the scope of the present invention, such as inverting the output level of the shift registers 23, 23a.

〔Effect of the invention〕

As described above, according to the hard logic type dot display signal generation circuit of the present invention, the capacity of the RAM of the waveform processing device is not made to correspond to the amplitude address Multi-bit luminance interpolation data, which performs luminance interpolation in the direction of the amplitude address based on both addresses, need only be stored as dot display data, making it possible to achieve a significant reduction in memory capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a dot display signal generation circuit according to the present invention, FIG. 2 is a block diagram of a dot display signal generation circuit according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of the circuit according to FIG. 2.

Claims (1)

[Claims] The dot display data of the waveform processing device, which samples the input waveform, performs linear and luminance interpolation, and stores it in RAM, is transferred to the dot display signal of the corresponding amplitude address on the display surface of the dot-type waveform display device at the time axis address. A dot display signal generation circuit for a dot-type waveform display device that sequentially converts each dot display data includes a latch circuit (1, 21) for a bottom address of dot display data, a latch circuit (1a, 21a) for a top address of the dot display data, It is obtained by counting the latch circuits (4, 24) for the bottom address side luminance interpolation data of the dot display data, the latch circuits (4a, 24a) for the top address side luminance interpolation data of the dot display data, and clocks. The count value of the amplitude direction address is the bottom address latch circuit (1, 21
) and a top address comparator (2, 22) that issues an output signal when the count value reaches the latch value of the top address latch circuit (1a, 21a). Comparator (2a, 22a
), a bottom address shift register (3, 23) whose increment by the clock is controlled by the output of the bottom address comparator (2, 22), and to which the bottom side luminance interpolation data is preset; a top address shift register (3a, 23a) whose increment by a clock is controlled by the output of the top address comparator (2a, 22a) and to which the top address side luminance interpolation data is preset; and both of the shift registers. and a gate circuit (5, 25) for generating an AND signal of the input signals between the bottom address and the top address by using the output signals of the input signals as both input signals, according to the number of bits of the luminance interpolation data. D/A converters (6, 2,
6) A dot display signal generation circuit characterized in that it is followed by the above.