SU1425685A1 - Program debugging device - Google Patents

Abstract

The invention relates to computing and is intended to enter and debug programs in a digital computer system. The purpose of the invention is to expand the field of application of the device. The device comprises an address decoder 1, an I / O node 2, a capture node 3, a bus matching node 4, a stop node 5. The use of the control microcomputer allows the user to extend the set of debugging functions by setting several debug modes in the format of one command word. 8 il. (WITH

Description

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The invention relates to computing and is intended to enter and debug programs in a digital computer system implemented on the basis of microprocessors (MP) and having a main structure.

The purpose of the invention is to expand the field of application of the device.

The program being debugged from a specific address, as well as reading and modifying the contents of the internal registers of the MP processor of the computer system being debugged (ICS), is carried out in the proposed device by means of memory simulation, sent to the interface bus of the interface processor interface from the programmable input-output node (UIP ) control signals are generated that logically disconnect the memory and I / O ports of the processor from the internal interface; in addition, they are replaced by an I / O port with The PVB node, the Controller of the microcomputer, enters the codes of the commands and operands into the data input port of the PVV node and, from the bus latching node, generates a transmit and receive signal (PDM), simulates the memory and I / O ports of the OVS processor, while MP The OBC processor, executing these commands, performs various debugging procedures: a transition to a delayed program at a certain address, input or output of its internal registers, etc. Data transfer between the data input / output port of the PVV node and the data bus interface of the processor OVS in this mode is carried out through the bus matching node in the presence of signals BB, VYV, SChT, CPD bus of the interface interface processor interface. The end of data broadcasting through the bus matching node is determined by the moment of the BB, TIP, CST, LPS signals of the control bus of the OVS processor, and not at the end of a certain time interval from the start of data broadcasting, Thu ensures more reliable operation of the OVS MP processor. Thus, the introduction of additional features allows to obtain a positive effect and satisfies the criterion of significant differences.

FIG. 1 shows a block diagram of a device for debugging.

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programJ in FIG. 2 is a functional diagram of an address decoder j in FIG. 3; a functional diagram of an I / O node; in FIG. 4 is a functional diagram of the gripping unit in FIG. 5 is a timing diagram of the operation of the gripping node; FIG. 6 is a functional diagram of the bus matching unit; FIG. 7 is a functional diagram of the stop unit; FIG. 8 is a block diagram of a debugging complex.

The device for debugging programs (Fig. 1) contains address decoder 1, I / O node 2, capture node 3, bus matching node 4, stop node 5, address bus 6 and control 7, data input bus 8, third group of inputs 9 node I / o, address bus 10, data 11, bus node 12 control, capture mode input 13, bus driver select input 14, stop mode input 15, capture node pickup mode output 16, capture bus assignment node output 17 , output 18 of the stop unit stop acknowledgment, output address bus 19, data 20, the control device 21.

The address decoder 1 is designed to identify the I / O ports of the device for debugging programs in the address space of the control microcomputer and contains (Fig. 2) a permanent memory element 22 and a delay element 23. Element 22 senses the decryption of bus address address signals 6 in the presence of explosive signals of control bus 7 and generates individual sampling signals (VB1-VBZ) at input 9 and the sms signal which passes through delay element 23 to control bus 7.

The I / O node 2 is designed to store information that controls the operation of the pickup node 3, bus 4 alignment and stop.5 when implementing debugging modes, as well as generating RAM prohibition signals (ZAPR1), prohibiting ROM (ZAPR2), and resetting (SVR a) bus 21 control. Node 2 contains (Fig. 3) parallel interface elements 24-26, each of which contains two eight-bit and two four-bit I / O ports, each of which can be programmed either for input or for output of information.

Capture node 3 is designed to implement the procedure for transferring control of address buses 19, data 20, control 21 from an all-purpose processor to a device for debugging programs. Capture node 3 (FIG. 4) contains a capture request trigger 27, a capture confirmation trigger 28, generator 29, AND 30, a capture request output 31, a capture acknowledgment input (PDT) 32 of the control bus 21, a capture mode confirmation output 16.

The bus matching unit 4 is designed for switching signals from bidirectional internal buses of address 10, data 11, control 12 and corresponding signals of bidirectional buses of address 19, data 20, control 21, and also for generating a PGHS signal in simulation mode. Node 4 (Fig. 6) contains bi-directional bus drivers (PF) data 33, addresses 34, control 35, data transfer confirmation trigger 36, PF selection trigger 37, data OR 38, data transfer inputs 39-41, input 42 Selection of ShF 34 and 35, input 43 of Selection ShF 33, 44 gating triggers 36 and 37.

Node 5 stop is designed to stop the operation of the processor OVS one of the predefined stop addresses and the condition of the exchange and

roEV 60. floppy disk 65 can also be used to store programs being debugged and intermediate debug results. The console 64 is intended for the user to enter command words that control the operation of the microcomputer 60 and the device 59 for debugging programs, as well as for entering a message to the research institutes formed during the debugging process. The debug protocol can be printed out 66.

The device for debugging programs has autonomous, control,

15 capture, stop, imitation.

In autonomous mode, the control microcomputer, by configuring the ports of node 2, sets the nodes of the capture 3, matching the buses 4, and stops 5 to the original

20 state, in this case all previously entered debug modes are canceled, the device for debugging the logic program programs is disconnected from address buses 19, data 20, control 21 and does not affect

25 to work processor OVS.

In the control mode, the control microcomputer, having entered information into port D5 of node 2, has the ability 30 to generate on the control bus 21 control signals CBP, ZAPR1, ZAPR2, which carry out the initial installation of the nodes of the OBC processor (CBP)

CPU interface connection

contains (FIG. 7) an element of RAM 45 compared with components of RAM (ZAPR1), components, multiplexer 46 of exchange conditions, ROMs (ZAPR2) included in mode co-driver 47, trigger 48 of memory processor 68 (FIG. eight),

va, shaper 49 short interface disconnect

pulse, element 50, input 51 of the OVS recording processor of the input-output ports 69 and input 52 of the comparison RAM 45, 40D (ZAPR2).

input 53 for selecting multiplexer 46, group of inputs 54 for selecting information input for multiplexer 46, inputs 55 and 56 for setting the mode, input 57 for canceling the stop mode, output 58 for stopping the operation of the OBC processor. 8 shows a device 59 for debugging programs, microcomputer 60, OVS 61, MP 62, memory 63, console 64, floppy disk drive 65, 66, MP 67 OVS, memory 68 OVS, ports 69 input-output.

The device works as follows.

All debugging procedures implemented by the device 59 for debugging programs are carried out under the control of the program loaded into memory 63 of the NSG 65 and executed by the MP 62 micV capture mode; the device 59 for debugging programs (Fig. 8) presents the user with the ability to exchange data memory 63 universal microcomputer 60 on the one hand, memory 68 and I / O ports 69 on the processor, on the other hand, and also read and modify memory 68 and I / O ports 69 in direct access mode. Entry of the capture mode is triggered by the port D7 signal at the output 13 of the PVB node 2 (FIG. 3). Entrance to the capture mode is confirmed by a signal at the output 16 of the capture unit 3, after which the microelectric computer adjusts the PFs 34 and 35 of the node 4 matching (Fig. 6) and the ports D1, D2 PWB (Fig. 3) to the output of the address and enters address information into them

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roEV 60. floppy disk 65 can also be used to store programs being debugged and intermediate debug results. The console 64 is intended for the user to enter command words that control the operation of the microcomputer 60 and the device 59 for debugging programs, as well as for entering a message to the research institutes formed during the debugging process. The debug protocol can be printed out 66.

The device for debugging programs has autonomous, control,

5 capture, stop, imitation.

In autonomous mode, the control microcomputer, by configuring the ports of node 2, sets the nodes of the capture 3, matching the buses 4, and stops 5 to the original

0 state, at that all previously entered debug modes are canceled, the device for debugging the logic program programs is disconnected from address buses 19, data 20, control 21 and does not affect

5 for the operation of the processor OVS.

In the control mode, the control, microcomputer, having entered information into port D5 of node 2, has the ability to 0 to generate on the control bus 21 control signals CBP, ZAPR1, ZAPR2, which carry out the initial installation of the nodes of the OBC processor (CBP)

In the capture mode, the device 59 for debugging programs (FIG. 8) provides the user with the ability to exchange data between the memory 63 of the universal microelev 60 on the one hand, the memory 68 and the I / O ports 69 of the processor on the other side, as well as read and modify memory 68 and I / O ports 69 in direct access mode. Entry of the capture mode is triggered by the port D7 signal at the output 13 of the PVB node 2 (FIG. 3). Entrance to the capture mode is confirmed by a signal at the output 16 of the capture unit 3, after which the microelectric computer adjusts the PFs 34 and 35 of the node 4 matching (Fig. 6) and the ports D1, D2 PWB (Fig. 3) to the output of the address and enters address information into them

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control, which goes respectively to address buses 10 and 19, and controls 12 and 21, Depending on the direction of data transfer, the FF 33 of the bus matching unit 4 and port 1) 3 of the data of the PWV node 2 are configured for either input or output. The memory 68 or ports 69 of the I / O processor processor in response to the call generate a QAP signal from the control bus 21 via the bus matching node 4 to the input 17 of the D4 port of No.2. In response to the PPD signal, the control microcomputer cancels the control information in port D2 of node 2, which causes the cancellation of the PDP signal and completes the exchange cycle. At. Cancellation of the capture mode is first carried out by turning off the FF 33-35 of node 4 bus alignment and 20 then the input signal of the capture mode at output 13 of node 2 is canceled.

In the shutdown mode, the program debugging device provides the user with a shutdown of 25 of the HOS processor based on the exchange condition and stop addresses, as well as on the coincidence of the condition and stop address specified in the command word format entered from the control console 64 of the microcomputer level (FIG. 8) The number of set stop addresses is not limited. The following bus signals 21 of the interface interface interface processor can be used as the exchange condition: BB, VYV, SCT, RFS, generated by MP 67 when accessing memory 68 and input ports 69 output — STEP generated in each cycle of command instruction selection; PDT formed by

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the implementation of direct access procedures in the interface of the processor, the implementation of the mode begins with the setup of the control microcomputer 60, stop node 5 through node 2, for this purpose the SchF 33-35 of the bus alignment node 4 are previously disabled. If in the command word format entered from the console .64 micro computers, the addresses of the points are restarted, then the ports D1 and D3 of node 3 are configured for output and micro computers, input of information about addresses, data and using port D6 of node 2, There is no entry in RAM 45 comparing first logical zeroes to all addresses, and then to addresses specified in the command word format - logical ones, then RAM, port D6 of node 2 multiplexer 46, adjust Q 0

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There is a choice of terms for the exchange specified in the command word format. Then, the ports D1-D3 of node 2 and PF 33-35 of node 4 of bus alignment are configured to input, in addition to address 10 bus, data 11, trans 12 control. the corresponding signals of the address bus 19, data 20, control 21, next, the control microcomputer 60 through the port D6 of node 2 are set, the triggers 47 of the node 5 stop are set to the appropriate state, it enters the stop mode and proceeds to analyze the stop mode confirmation signal the output 18 of the stop node 5 formed when the address code on the address bus 19 matches and the exchange conditions on the control bus 21 with those specified in the command word format. When confirming the stop mode, a message is displayed on the console 64 of the microcomputer, containing information on the status of the bus address 19, data 20, control 21 and the interface of the SIS. Then the user from the 64 microelec console enters a control word that controls either the transition to the new, next stop point in the stop mode, or the end of the stop mode. To go to the next microcomputer breakpoint via port D6 of node 2, it either disconnects or selects the comparison RAM 45, sets up the multiplexer 46 to choose the CONDITIONS of exchange in accordance with the parameters of the control word, sets the stop trigger 38 to the O state, and operation of the processor OVS according to the executed program. When canceling the stop mode of the microcomputer through the port D7 of node 2, turns off the SchF 33-35 of the node 4 for tire scaling, and through the port D6 of node 2 sets the triggers 48 and 47 to the state O,

In the simulation mode, the device for debugging programs allows the user to start the operation of the processor from any address, and also to read and modify the contents of the internal registers MP 67 of the processor of the interface, when implementing this mode, memory 68 I and ports 69 the output of the SIS processor is replaced by the I / O port D3 of the node 2 of the device for debugging programs, through which the control micro-computer 60 provides the execution

The MP 67 of the processor of the OVS of commands and programs recorded in the memory of 63 micro-EB can be, for example, an unconditional jump command to an address, a program for outputting the contents of the internal registers MP 67, etc. In order to implement the simulation mode, the control microcomputer first enters a stop mode with stopping the operation of the OVS processor in the read cycle of the instruction of the next command. Then, the ZAPR1 and ZAPR2 signals are formed through the port D5 of node 2 (Fig. 3) to the control bus 21, and the memory 68 and the I / O ports 69 of the OVS processor are logically disconnected from the interface of the OVS processor and do not generate an FPA signal when they are accessed. bus 21 control.

Then, the ports D1 and D2 of node 2 and ShF 34 and 35 of node 4 of bus alignment are configured to enter information into port D3 of node 2 and ShF 33 of node 4, depending on the control signal of the BB, OUV, CST, BPS control 21 or input or output information. Next, through port D7 of node 2, triggers 36 and 37 of node 4 of bus alignment are set at input 44 to state O, the FF 33 is selected, and an FP signal is generated to the control bus 21 of the interface of the OVS processor. Then, the stop unit 5 is configured to stop the operation of the SIS processor in the next cycle and starts the operation of the SIS processor with the Start signal at input 57 of the stop unit 5 (Fig. 7). The MP 67 of the OVS processor, having received the RPM signal, terminates this cycle of operation, stopping the formation of the signals BB, VBV, CST, BPS to the control bus 21, while the triggers 36 and 37 of the bus alignment unit 4 are set to state 1, the DIO 33 is turned off and the formation of the PDM signal ceases. In the next cycle, the node 5 stop again stops the processor, the SIS, and if the execution of the simulated command or program is not completed, the transition to the next setting of the port D3 of node 2 and PF 33 of the node 4 bus alignment is made. When canceling the imitation mode, the microcomputer removes the ZAPR1, ZAPR2 signals of the control bus 21, disables the FF 33-35 of the bus alignment node 4, cancels the

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stop, and the processor OVS proceeds to the execution of the program being debugged, located in memory 68 of the processor OVS.

Claims (1)

Invention Formula A device for debugging programs containing an address decoder and an I / O node, with the first and second groups of information inputs of the address decoder and I / O node respectively connected to the address and control buses of the device for connecting to the control computer of the same name, the third group of information inputs the outputs of the I / O node are connected to the data bus of the device for connecting to the data bus of the control computer, a fourth group and the information inputs of the node of the input and output link are connected to the output group of the decoder address, characterized in that, in order to expand the scope of application, the device comprises a gripping node, a bus matching node and a halting node, the output of the capture mode of the I / O node is connected to the input of the capture mode, the capture confirmation output of which is connected to the corresponding input I / O, bus and data address and control of the I / O node are connected to the corresponding buses of the bus matching and stopping nodes, the output of the data transfer confirmation of the bus matching node is connected to the input of the same name I / O bus, bus selector bus selector bus node connected to the I / O node bus of the same name, input stop command set group of the stop node is connected to the I / O node mode setting output group, connection stop stop confirmation output; the corresponding input I / O node, address bus and data of the bus matching node are bi-directional device buses for connecting to the corresponding buses of the debugging system, the control bus of the gripping node, the bus matching node, the stop node and the I / O node form a bi-directional device bus for connecting to the control bus of the debugging system. nnflnfinnnnnnnnn, r J-A 7 //////////// Editor I. Shulla Fia.8 Compiled by I.Safronova Tehred A. Kravchuk Proofreader V. But ha