CN218450079U

CN218450079U - STM32 one-key downloading circuit based on CH340G

Info

Publication number: CN218450079U
Application number: CN202222686178.9U
Authority: CN
Inventors: 陈晓明; 王昱尧; 汤致和
Original assignee: Xuanqi Nanjing 3d Technology Co ltd
Current assignee: Xuanqi Nanjing 3d Technology Co ltd
Priority date: 2022-10-12
Filing date: 2022-10-12
Publication date: 2023-02-03
Anticipated expiration: 2032-10-12

Abstract

The utility model discloses a CH 340G-based one-key downloading circuit for STM32 series single-chip microcomputers, which relates to ISP one-key downloading of STM 32; the system comprises an STM32 single chip microcomputer, an ISP download module and a control circuit of a DTR and an RTS to the single chip microcomputer RESET and BOOT0, wherein a DTR pin of U2 is directly connected with the single chip microcomputer RESET pin, the RTS pin of U2 is connected to a grid of Q1 through a resistor R3, a drain of Q1 is connected to the BOOT0 pin of the single chip microcomputer through the resistor R2, meanwhile, the grid is also connected to VCC through the resistor R1, and a source electrode of Q1 is grounded. The utility model discloses can use less components and parts to realize the function of downloading of a key of STM32 series singlechip, reduce BOM complexity, effectively save veneer cost and on-board space to save the batch cost.

Description

STM32 one-key downloading circuit based on CH340G

Technical Field

The application relates to an ISP one-key downloading circuit aiming at an STM32 series single chip microcomputer based on CH 340G.

Background

STM32 series single-chip microcomputer of Italian semiconductor company is a programmable micro control chip, a program needs to be compiled and then downloaded into FLASH inside the chip, the chip completes corresponding actions according to code indication, the application is extremely wide, the body shadow of various Internet of things products or automatically controlled electromechanical products can be seen, and the current program is downloaded into the chip and has three interfaces, namely JTAG, SWD and ISP; the ISP downloading only needs to occupy two IO ports as data interfaces, and after the program is downloaded, the two IO ports can be released to be used by the chip.

When an STM32 series chip normally runs an on-chip program, a BOOT0 pin needs to be at a low potential, a RESET pin needs to be at a high potential, an ISP (internet service provider) downloads the program from the chip through a USB (universal serial bus) to a TTL (transistor-transistor logic) device, the BOOT0 pin needs to be restored to a low level after downloading, the program normally runs according to one-time resetting after being downloaded, the downloading process is relatively complicated, two solutions to the problem are proposed on the market aiming at the problem, the two solutions are mentioned in a utility model with an authorization publication number of CN 210488536U, and actually, two one-key downloading circuits based on the downloading are adopted on STM32 development boards of a field fire and a normal point atom, which are respectively shown in a figure 1 and a figure 2 and a figure 3, wherein the figure 1 is a normal point atom adopting scheme, and the figure 2 and the figure 3 are field fire adopting schemes. The low level reset of setting DTR in the software that need cooperate ISP to download, RTS high level advances BootLoader, and these two kinds of a key download circuit are comparatively complicated, and components and parts are more, increase BOM cost. The cost difference of the single plates is not large, but the increased cost is not negligible for mass production.

SUMMERY OF THE UTILITY MODEL

An STM32 one-key downloading circuit based on CH340G comprises an STM32 series single chip microcomputer and an ISP one-key downloading module; the connection mode of ISP download module and STM32 series single chip microcomputer is characterized in that: a control circuit of a RESET and BOOT0 pin of the single chip microcomputer by DTR and RTS is added between the ISP downloading module and the single chip microcomputer;

preferably, the control circuit is used for controlling the electric potentials of two pins of the RESET and the BOOT0 to meet the condition of ISP one-key downloading, and the DTR and the RTS are used for controlling the structure of the control circuit of the pins of the RESET and the BOOT0 of the singlechip;

preferably, in the control circuit, the DTR pin of U2 is directly connected to the RESET pin of the single chip, the RTS pin of U2 is connected to the gate of Q1 through a resistor R3, the drain of Q1 is connected to the BOOT0 pin of the single chip through a resistor R2, the gate is also connected to VCC through a resistor R1, and the source of Q1 is grounded.

Preferably, the single chip microcomputer is an STM32 series single chip microcomputer, the actual verification chip is an STM32F103C8T6 single chip microcomputer, the chip U2 is CH340G, and the Q1 is an N-channel MOS transistor or an NPN-type triode.

The utility model discloses the advantage:

1. compared with other two kinds of download interfaces of STM32, the novel use adopts ISP download, does not need additional download debugging tools, saves the cost of downloading the debugging tools, and releases two occupied IO interfaces for the continuous use of the singlechip after the program download is finished;

2. compared with the traditional ISP downloading, the utility model realizes one-key downloading without manually switching the jumper cap of BOOT0 and manually pressing the reset switch;

3. compared with the existing one-key downloading technology in the market, the method has the characteristics of simple structure, fewer components, cost saving and board space saving.

Drawings

FIG. 1 is a portion of a conventional ISP download circuit for a punctual atomic adoption scheme;

FIG. 2 is a USB to TTL circuit for a wildfire adoption scheme;

fig. 3 is an ISP one-touch download circuit for a wildfire adoption scheme:

FIG. 4 is a technical solution diagram of the present invention;

FIG. 5 is a download success interface using FlyMcu;

FIG. 6 is a waveform of change in downloading when a low level of DTR is reset and RTS is high level enters BootLoader;

fig. 7 is a waveform of a change in downloading when "DTR high level reset" and RTS high level goes to BootLoader.

Detailed Description

The utility model aims to realize the ISP key download function of STM32 series singlechip with less components and parts to realize the function of key download, also can the effective control veneer cost simultaneously, thereby save the batch cost.

The technical scheme of the utility model: a CH 340G-based STM32 series single-chip microcomputer one-key downloading circuit is characterized in that a circuit part can be realized by only adding four components on a traditional ISP downloading circuit, as shown in figure 4.

The circuit structure is as follows: as shown in fig. 4, the RESET pin of the chip is connected to pin No. 13 of CH340G, i.e., DTR pin; BOOT0 is connected to the drain of Q1 in the figure through a resistor of 10k ohms, meanwhile, the drain of Q1 is pulled up through a resistor of 10k ohms, and the source of Q1 is grounded. Q1 is an N-channel MOS tube and can be replaced by an NPN type triode, wherein R3 only plays a role in current limiting protection, and through material object verification, the Q1 can be omitted when being an MOS tube, and one-key downloading of a program is not influenced; in addition, the circuit needs to be matched with ISP downloading software to set 'DTR high level reset, RTS high level input BootLoader', which is different from the scheme of punctual atoms and wildfires, and a successful downloading interface using FlyMcu is shown in FIG. 5.

The realization principle is as follows: the ISP download of STM32 needs to go from low potential to high potential through BOOT0, RESET goes from high potential to low potential and then goes to high potential, finally BOOT0 goes back to low potential, and the DTR and RTS pins of CH340 can be set by software, so that it is possible to configure a one-key download circuit to implement a one-key download function by setting different states of DTR and RTS, through detection, the DTR and RTS pins of CH340G are both in high level position in normal state, when setting "low level RESET of DTR, RTS high level enters BootLoader", the waveform change in the download process is as shown in fig. 6, the high potential of DTR and RTS pins is converted into low potential, during which one-key download circuit generates one-time high potential pulse, and during which one-key download circuit of atom and wildfire can implement one-key download function, which is not described in detail here, the new type is used to set "DTR high level RESET, RTS high level enters BootLoader", the waveform change in the download process is as shown in fig. 7, during which, the low potential pulse of DTR has two times. The circuit of the utility model is combined to know that, because the chip RESET pin is directly connected with the DTR pin of CH340G, when the DTR pin is high potential, the chip RESET pin is high potential and is in a normal operation state, and when the DTR outputs low potential pulse, the chip RESET pin is pulled down and is RESET once and recovered; when RTS is low potential, the grid of Q1 is low potential, the NMOS tube is disconnected, BOOT0 is pulled up to high potential by R1 and R2, when RTS is high potential, the source and drain of the NMOS tube are conducted, the drain potential of the NMOS tube is pulled down, at the moment, BOOT0 is pulled down to low potential by R2, and the chip recovers to normal operation mode. The whole downloading process passes through the process that BOOT0 goes from low potential to high potential, RESET goes from high potential to low potential and then goes back to high potential, and finally BOOT0 goes back to low potential, so that the requirement of chip ISP downloading is met, and actual tests show that the circuit can smoothly realize the ISP one-key downloading function of STM32 series chips.

Claims

1. An STM32 one-key downloading circuit based on CH340G comprises an STM32 series single chip microcomputer and an ISP one-key downloading module; the connection mode of ISP download module and STM32 series single chip microcomputer is characterized in that: a control circuit of a RESET and BOOT0 pin of the single chip microcomputer by DTR and RTS is added between the ISP downloading module and the single chip microcomputer;

the control circuit is used for controlling the potential of two pins of the RESET pin and the BOOT0 pin to meet the condition of ISP one-key downloading, and the DTR and the RTS are used for controlling the control circuit structure of the RESET pin and the BOOT0 pin of the singlechip;

in the control circuit, a DTR pin of U2 is directly connected with a RESET pin of a singlechip, an RTS pin of U2 is connected to a grid electrode of Q1 through a resistor R3, a drain electrode of Q1 is connected to a BOOT0 pin of the singlechip through a resistor R2, the grid electrode is also connected to VCC through the resistor R1, and a source electrode of Q1 is grounded.

2. The CH 340G-based STM32 one-key download circuit of claim 1, wherein: the single-chip microcomputer is an STM32 series single-chip microcomputer, the actual verification chip model is an STM32F103C8T6 single-chip microcomputer, the chip U2 model is CH340G, and Q1 is an N-channel MOS tube or an NPN type triode.