SU1401518A1 - Associative memory - Google Patents

Abstract

The invention relates to computing, in particular, to information storage devices, and is intended for high-performance systems with the possibility of parallel associative information processing. The purpose of the invention is to increase the speed of the device when performing an associative search on the criterion "the nearest greater (smaller) to the given. The device contains an associative memory block, a search flag register, a mask register, an OR element, a switch, a search sign modification block consisting of n code converters (n is the number of processed numbers), a control block. 4 il.

Description

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The invention relates to computing technology, in particular, to information storage devices, and is intended for high-performance computing systems with the possibility of parallel associative information processing.

The purpose of the invention is to increase the speed of the device when performing an associative search on the criterion "the nearest greater (smaller) to the given.

FIG. 1 shows a schematic diagram of an associative memory device; in fig. 2 is a block diagram of a code converter; in fig. 3 is a block diagram of the control unit; in fig. 4 - timing charts of the device.

The associative memory device (Fig. 1) contains an associative memory block 1, a search characteristic register 2, a mask register 3, an OR element 4.

Unit 1 has address input 5, the first group of information inputs 6, the first group of information outputs 7.

The second group of information inputs 8 of the device and the second group of information outputs 9 of the device are connected respectively to one of the information outputs of the switch 10 and the outputs of register 2. The outputs of register 2 are connected to information inputs lli-11 "of the search attribute modification block 12 (n is the width of the data being processed ). Inputs 13i-13 "intermediate values of the characteristic of the block 12 are connected to the information outputs of the buffer register 14, the information outputs of which are connected to the outputs 15i -15" of the intermediate values of the characteristic of the block 12. Information outputs 16i - 16l of the block 12 are connected to the information inputs of the switch 10.

Block 12 contains n converters 17 | - 7p codes, and the output 18, - transfer (, n-1) of the converter 17 / is connected to the master input (j + l) -ro of the converter 17 / + I. Log 19 | connected to logical potential source 20.

The device also contains a control block 21 having an entry Search result 22, an input End of modification 23 an entry End of search 24, and an input Start getting 25. Block 21 has exits 26-28. The output 28 of the block 21 is connected to the inputs 29i - 29 of the control of the reception of the block 12. The block 21 also has the outputs 30-33. Outputs 32 and 33 are, respectively, outputs "Word found and" Word not found device.

The device search mode input 34 is connected to the search type control input inputs 35i-35 of block 12. Inputs 36 and 37 of block 1 are a write input and a read input of the device, respectively.

Each transducer 17 (FIG. 2) contains the element UNEQUAL DIFFERENCE 38, the output connected directly to

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the input element AND 39 and through the element NOT 40 - with the input element AND 41, the element OR 42, the element UNACTIMATE 43.

The control unit 21 may be implemented as a firmware control device or as a control machine with rigid logic. One of the possible options for the implementation of block 21 in the form of a control automaton (Fig. 3) contains a trigger 44, elements AND 45 and 46, an element OR 47, a trigger 48, elements And 49 and 50, a trigger 51, elements And 52 and 53, an element OR 54, trigger 55, element And 56, trigger 57, element And 58, trigger 59, elements AND 60 and 61, elements NOT 62-64, elements OR 65-67, synchronization input 68.

The device works as follows.

In the initial state, in block 1, n binary binary numbers are stored.

The process of associative search for the number closest to the given one begins with a single signal to the input 25 of the block

21, by applying a signal to the device input 34 (a single signal — when searching for the nearest larger signal to the specified and zero signal — when searching for the nearest smaller signal to the specified signal), feeding the specified number to the device inputs 8. A single signal at input 25 of control unit 21 initiates the formation by unit 21 of single signals at outputs 26 and 27 (Fig. 4, cycle 1), which control the passage of a binary code of a given number from inputs 8 through switch 10 to inputs of register 2, receiving of the new code to register 2, installation of registers 3 and 14 to the initial state (in the initial state of register 3 all its bits are set to one, and in the initial state of register 14 all its bits, except the youngest, are set to zero, and the youngest is set to one). Thus, on register 2, the given word is fixed, and all bits of register 3 will be set to one, which corresponds to the absence of masking.

In the next cycle, the control unit 21 generates a single signal at the output 30, which initiates a poll of all the cells of block 1 with a given number code. If among the numbers stored in block 1 there is at least one that matches the given one, then, naturally, it will be the closest one and at the corresponding output of block 1 a single level signal will be generated, which through the OR 4 element goes to the input

22 of the control unit 21, which generates at its output 33 a signal of the successful end of the search operation. The code of the number closest to the given one is removed from the information outputs 9 of the device.

If among the numbers stored in the block 1 there are no coinciding with the given one, then the further course of the search procedure depends on what the nearest larger or nearest smaller one looks for.

The search for the closest one to the specified is carried out as follows.

In the next cycle following polling of block 1, control block 21 generates single signals at outputs 27 and 28. The first of these signals receives a code from outputs 16 of block 12 through switch 0 open to zero from output 26 of switch 2 to register 2, the second of which permits setting in “About the bits of the register 3 masks marked with units of code taken from the outputs 18 of block 12, and initiates the reception of the code from the outputs 15 of block 12 to the register 14.

The code taken from the outputs 16i -16 ' of block 12 is generated as follows. The signal at output 16 ((i 1, p) corresponds to the signal at the input I, -, if, where d is the number of the bit (starting with the lower ones) in which the code at the inputs 111 -11 "contains the first (starting with the lower order bits) zero, otherwise () the signal at output 16 / is the inverse of the signal applied to input 11. For example, if code 111101011 is inputted to input 11 (in the above record, the least significant bit is to the right,,), then output 16i is 16l, code 01101100 is formed (inverted bits are marked).

The conversion considered is as follows. The signal at input 11, converter 17, is inverted by the EQUIDITY element 43 / if there are single signals at inputs 13, - or 19 ,. In particular, since the input signal I3i receives a single signal from the lower bit of register 14, a signal is generated at the output 16i that is inverse to that supplied to the input P At the output of the element EQUAL VALUE 38, the signal of the unit level is generated if it is input 11; Zero is applied when searching for the nearest major (one is fed to the input 35t), and otherwise, when searching for the nearest smaller one (zero is input to the input 35 /). Accordingly, if a single potential signal is applied to the input 111, a single level signal will be generated at the output 18i, which is fed to the input of the setting in the “O” low bit of the mask register 3 and to the input 102 of the next converter 172.

Conversions similar to those in converter 17i occur sequentially in the second, third, and so on. converters x17 up to d-ro, to which input 7d is zero, the closing moment is 41rf, so that the signal at output 18d has zero potential and does not initiate the work of subsequent converters

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17. At the output 15 of the converter, a single signal is formed, which writes the unit to the d-th bit of the register 14. Thus, in the framework of the given example, the codes 11111100 and 00000100 are fixed on the register 3 and the register 14.

In the next cycle, the signal from the output 30 of the control block 21 initiates polling of the block 1. In block 1, there is not a single word that matches the contents of register 2, the output of the OR element 4 and the input 22 of block 21 retains the potential of zero level . Block 21 generates signals at outputs 27 and 28.

Registers 2, 3 and 14 from the corresponding outputs of block 12 of the polling code are assigned codes generated by the described method, and the value dg, the position number of the second zero in a given word, plays the role d. So, under the conditions of the above example, d2 5, and the codes fed to registers 2, 3 and 14 are respectively: 01110000, 11110000, 0010000. If in the current code conversion cycle a signal is generated at the output 18 of the high converter 17, which corresponds to If the code does not contain the specified number of zeros that were not transformed in the previous cycles, then the control unit 21 generates a single signal at output 32, which indicates that among the numbers stored in the accumulator there are no numbers greater than the specified one.

After each cycle of converting the contents of registers 2, 3 and 14, block 1 is interrogated. This procedure continues until a signal appears at output 32 or input 22 of control block 21. In the second case, the control unit 21 will generate a shift signal to the right of the contents of registers 3 and 14 (FIG. 4, cycle 7) at its output 31, and then generate a polling signal at its output 30. If the result of polling of block 1 is negative (i.e. the input 22 of the control unit 21 is saved a zero signal), the contents of the register 2 is corrected by receiving the register 2 from the outputs 16 of the unit 12 (the control unit 21 generates signals on its outputs 27). The code indicated is different from the code on the inputs 11 by the inverse value of one bit, the position of which is determined by the unit in register 14.

After correction, the considered cycle repeats again, including shifting the contents of registers 3 and 14 to the right, polling block 1 and, if necessary, correcting the contents of register 2. The last cycle is a cycle in which, in the low-order bit of register 14, a unit appears Arriving at the input 24 of the control unit 21, initiates the appearance of a signal of a successful end of the operation at the output 33.

Claims (1)

Invention Formula An associative memory device containing an associative memory block, a search flag register, a mask register, an OR element, a buffer register, and a control block, wherein the search result outputs of the associative memory block are connected to the inputs of the OR element, whose output is connected to the , the output of the lower part of the buffer register is connected to the input "End of the search of the control unit, input" The start of the operation of the control unit is the device start input, the first output of the control unit is connected to The search register control input register, whose bit outputs are connected to the search inputs of the memory block and are information outputs of the first device group, the mask register bit outputs are connected to the associative memory block masking inputs, the second control block output is connected to the shift control input to the right of the buffer register and to the input of the shift control to the right of the mask register, the third output of the control unit is connected to the search control input of the associative memory; the address input of the associative memory block is the address input of the device, the information inputs of the associative memory block are the information inputs of the second group of the device, the write control input and the read control input of the associative memory block are respectively the write input and the read input of the device, the information outputs of the block the associative memory is the information output of the second group of the device, the fourth and fifth outputs of the control unit are respectively output Home Word is found and output Word No device found, characterized by the purpose of increasing the device speed, a search indication modification block and a switch are entered into it, the outputs of which are connected to the inputs of the search indication register, the outputs of which are connected to the information inputs of the search attribute modification block, the information outputs of which are connected to the information inputs of the first group of the switch, the information inputs of the second group of the switch are the information inputs of the second group of the device , outputs and intermediate values inputs 5 signs of the search tag modification block are connected respectively to the information inputs and outputs of the buffer register, the setup input of the tag modification block is connected to the potential source of a logical zero, the search type search control input of the search sign modification block is an input of the device search mode, search masking control outputs of the search sign block connected to the installation inputs in the "About register bit register of the mask; the sixth output of the control unit is connected to the input of the receive control of the buffer register Stra and to the input of the control technique of feature modification search block, one of the control outputs which maksirovaniem 0 is connected to the input "End of the modification of the control unit, the seventh output of the control unit is connected to the control input of the switch, to the installation inputs in" About the bits of the buffer register, except the low-order bit, to the input of the buffer register, to the installation input to "1 mask register The installation enable input in the "About” bits of the register of the mask is connected to the sixth output of the control unit. 0 five five 27 Zg 35 Vus.l Hofiefl / 77l7 / / 77 (7 123 56183 S 11 1Z 13 7 75 % 0 r n ln A / A %one A p l a f //. 4