SU1277211A1 - Associative storage - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices. The aim of the invention is to increase the speed of the device when searching for Hamming words closest to the polling attribute. The device contains an accumulator, a poll register, a control unit, the first group of elements UNACTIFICATION, the search result register, as well as newly entered shift signal formers, elements PfflH, elements OR NOT, the second group of elements UNABLE, and the shift matrix, each cell of which contains a trigger and the item is NOT. The increase in speed is achieved due to the fact that the words stored in the accumulator and the bits of the polling feature are divided into two main parts, the processing of which is conducted in parallel. The bit slices are selected sequentially from the accumulator, the values of which are compared in the UNEQUALITY elements with the interrogation sign. If there is a mismatch in the corresponding row of the shift matrix, the previously set zero values are shifted, for example, to the right (L values and writing to the leftmost cell of the unit value. The required words correspond to the unit values in the cells of the rightmost column of the shifting matrix. The speed increase is also achieved due to reducing the time required to shift the values in the matrix and by allocating the desired number per cycle. 1 Cp f-crystals, 4 sludge, 1 tab.

Description

The invention relates to computing, in particular, to storage devices.

The purpose of the invention is to increase the speed of the device when searching for Hamming closest words to a poll sign.

FIG. 1 shows the functional scheme of the proposed device; in fig. 2 - functional diagram of the storage cell matriizets. in fig. 3 are functional diagrams of the most preferred embodiments of the control unit and the shift signal generator, respectively.

The proposed device contains (Fig. 1) control block 1, drive 2, polling register 3, first 4 and second 5 groups of UNEMBURN elements, shift signal formers 6, shifting matrix 7, search result register 8 with input 9. In FIG. 1, the cells of the shifting matrix 1 1 are indicated. 1. The device also contains the elements of the WIT 11, the ILINE 12 elements, the output buses are 13 rows, the output tires are 14 columns of the shifting matrix 7.

The shifting matrix 7 contains the first 15 and second 16 groups of load elements. FIG. 1 denotes a power bus 17, exits 18-23 of control unit 1. Each cell 10 of the shift matrix 7 contains (Fig. 2) trigger 24 and the element NOT 25.

The control unit 1 contains (Fig. 3 the decoder 26, the microprogram matrix 27, the micro-command register 28, the operation code register 29 and the clock signal generator 30.

Shaper 6 shift signals contains (Fig. 4) elements AND-NOT 3134, trigger 35 and element 1-SHI-NO 36.

Argument array words are stored in the storage cells of accumulated gel 2, and the polling flag is in register 3, and M is the bit word argument and the polling flag are divided into two equal parts and the highest bits are written in one part (for example, the left). There are two words of argument and a sign of the survey, and in the other - their second categories. Further partitioning of L, the bit argument word and the polling attribute, leads to a considerable complication of the design of the formers 6, which makes it difficult to fulfill the requirements set forth below for them. The storage cells of drive 2 and register 3 may have a different design (static or dynamic memory, shift registers, memory on a CMD, tracks of rotating magnetic memories, etc.). However, they must provide sequential bitwise circulation, namely: when the next control pulse arrives at the inputs of the register 3 and accumulator 2, the next bits of the left and right parts of this data are simultaneously read from the outputs of each memory cell. cells The number of cells 10 in the row of the matrix 7

M equals

The proposed device works as follows.

When a search command arrives at the inputs of block 1 (Fig. 1), block 1 generates the following sequence of operations. In the first microcommand, at outputs 20, 22 and 23, the following is formed: in code 20, a signal (logical unit) that does not interfere with the normal operation of the formers 6; at output 22, a signal (logical unit) that sets 1 of all bits of the register to 1

formers 6 and cells 10 mat0 8, test 7; at output 23, a signal (logical unit) prohibiting the search for a row of matrix 7 having the maximum number of ones.

Then, in a series of consecutive microinstructions, a series of signals is output at outputs 18, 19 and 21. As a result, sequential selection occurs from accumulator 2 of all bit sections (separate groups of lower and higher bits) of the array of argument words with synchronous sampling of the corresponding register bits 3 The bits of all P words (for each word, two bits are selected: one from the group of the youngest and the other from the rpynm.i of the older ones) come from drive 2 to the first inputs of the corresponding elements INEQUALITY 4, 5, and the least significant bits go to input DIMENSIONS, and the most significant bits go to the inputs of the UNSIMIZABILITY 5. Elements of the same way from register 3 receive the corresponding younger ones. The leading bits are the inputs of all the elements UNEMNATABILITY 4, and the higher bits are the inputs of the elements UNIMQUENESS 5. For those words where the value of a bit coincides with the value of the corresponding bit of the polling feature, the outputs of the corresponding elements are UNIMQUALITY 4 or 5 zero-level signals are generated, which are fed to the inputs of the corresponding driver 6, each of which operates in accordance with the table. The delay of the signal in the driver 6 must be equal to: the delay of the signal during the shift in the row of the matrix 7. The signal arriving at the inputs of the drivers 6 from output 21 ensures that the driver 6 and the matrix 7, i.e. At that time, when the matrix 7 processes the signal of one clock cycle, the drivers 6 process the signal of the subsequent clock cycle. If the output of the Kth (K 1, P) of the former 6 generates a shift resolution signal (logical unit) arriving at the synchronization inputs of all the cells of the 10th row of the matrix 7, then in this row the contents of the cells 10 will shift by one the bit to the right, and in the free, for example, the leftmost cell 10 of this line is written 1, otherwise the contents of the line 10 of the cells 10 of the matrix 7 will not change. At the end of the series of M + 1; -th signals generated at the outputs 18 and 19, at the output 20 a signal (O) is formed, which, arriving at the first inputs of the drivers 6, generates at its outputs a shift resolution signal ( 1) if in trigger 35 (FIG. 4) of this driver 6 was stored 1, and the prohibit signal is otherwise. At (-J- +2) -th cycle from output 21, a signal (O) is received, which prohibits the formation of shift resolution signals at the outputs of the formers 6, and from output 23, a signal is received allowing the matrix 7, containing the maximum number of units, to be released, t. e. highlighting a word that is most consistent with a poll sign. The insertion occurs in, M ", (, - + clock) and is reduced to setting (by signals coming from the outputs of the corresponding elements OR 11) in O all cells 10, except cells 10 of the column of matrix 7, in which the right 1 itself is contained, in which the indicated 1 corresponds to the word closest to the polling attribute according to the Hamming criterion. i.e. the word nearest to hemming to sign of the survey. It should be noted that is generally an array argument can contain several words having the same minimum code distance with respect to the interrogation attribute, and these words may be the same (then a mismatch occurs in the same bits) or different (mismatch in different bits). All these words correspond to the same number 1 in the corresponding rows of the matrix 7, where they are allocated in parallel. If necessary, masking of random bits of accumulator 2 can be introduced into the proposed device by known means, while it is possible to perform all the above operations only on undisclosed discharge sections. The increase in speed is achieved by dividing the argument words and the query tag into two equal parts and their parallel processing when performing the search operation for the words closest to Heh {shortage to the query tag, as well as reducing 1 time required for shifting information in the row of matrix 7 and due to the fact that the allocation of the desired number in the matrix 7 takes one cycle

Claims (2)

Formula from a mixture 1, An associative memory device comprising a poll register, a drive, a first group of items UNIMQUAL, a search result register and a control unit, one of whose outputs is connected to the control inputs of the poll register, a search result register and a drive, one of the outputs of which is connected to the first inputs elements of the UNEQUALITY of the first group, the second inputs of which are connected to the first output of the polling register, characterized in that, in order to increase the speed of the device when searching for words, the next x Hamming basis to poll it or incorporated elements, elements NOR second group elements unequal, conditioners shift signals .; and a shifting matrix whose input busbars of the columns are connected to the outputs of the OR elements, the first inputs of which are connected to the outputs of the OR-NOT elements, the first input of each of them is connected to the output bus of the corresponding column of the shifting matrix, and the second input of each element OR NOT, except the last - for weekend tires subsequent columns of the shift matrix, the input lines of which are connected to the outputs of the formers the shift signals, the first and second inputs of which are connected respectively to the outputs of the UNEQUAL EQUITY elements of the first and second groups, the first inputs of the UNEQUALITY elements of the second group are connected to the second outputs of the storage device, and the second inputs are connected to the second output of the polling register, the output buses of the shift matrix lines are connected to the inputs the poll result register, the control input of which is connected to the second inputs of the OR elements and the third inputs of the shift signal formers, the fourth and fifth inputs of which are the third and ode Ilin elements respectively connected to the other output control unit, the second input of NOR elementa.ILI latter is connected to the power schine. 2. The device according to claim 1, wherein the shifting matrix contains triggers, NOT elements and load elements, the first terminals of which are connected to the power bar, and the synchronization inputs of the trigger lines and the information inputs of the triggers of the matrix column are connected to the input matrix matrix rows, the trigger inputs of the column trigger are connected to the input bus of the matrix column; qi, the first output of each trigger in the row is connected to the information input of the next trigger in the row and the input of the NOT element whose output ene to output bus lines, the second outputs of flip-flops in a column are connected to the column output line, the second terminals of one of the load elements are connected to output lines of buses, and second terminals of the load elements to the other output asserted column lines. "about one g, "five , rgeEgEg 1 „ -P-L | 1-q L-rji j.ti 1 ± J "-I F ITU; 1 R I -U fn 4J1 in fil I iCj - ". one -rc ... .-4f L, J   "  Hfr Tl | :: r " J ffl one c F 11 J i one i: b / . Ebl : h M "N ky li KZ ii 55 op irh Th t J Thats OmW (from 6 J m / fO-j- 2 / From 6 an 91 25 I oKW I .J .2