SU1394218A1 - Device for evaluation of linear algebraic equation system - Google Patents

Abstract

The invention relates to computing, in particular to specialized computing devices, and can be used to process information in real. timescale. The purpose of the invention is to increase speed. The goal is achieved by the fact that the device contains and (where p is the order of a linear algebraic system of equations) inputs of 1 coefficients and free members of systems 1 of linear algebraic equations, n outputs 2 results, k blocks of 3 calculations (where k is the number of iterations), the first and, the second inputs are 4 and 5 synchronization, each block of 3 calculations contains n operational nodes 6.1 F.-f-ly, 2 silt, 1 tab. i (L

Description

The invention relates to computing and can be applied in the construction of specialized and problem-oriented processors for solving systems of linear equations.

The purpose of the invention is to increase speed.

FIG. 1 shows the structure of the device; in fig. 2 is a diagram of an operational node.

The device contains n inputs of 1 coefficients and free members, where n is the order of the linear system

algebraic equations, n outputs 2 of the result, k blocks of 3 calculations where k is the number of iterations, the first 4 and second 5 synchronization inputs. Each calculation unit 3 contains n operational nodes 6, with each operational node 6 containing (n + 1) registers 7, output register 8, register 9 locks, adder 10, first 11 and second 12 multiplexers, (n + 2) th register 13, element I 14, three groups of elements I. 15 - 17, control input 18, first 19 and second 20 outputs.

 The algorithm of operation of the device for solving systems of linear equations of the order in is based on the linear one-step interactional nonstationary method, which is presented as follows:

(one)

 - -n.-SAX - -c)

or

1:; - one

, (2)

where is vector nev zok

i-th iteration; X - vector i-x approximations of unknown systems;

Н - linear operator of the form

(J c (i)

(ib

Hpdiag (7. Ri - - Tn) - (3)

Here, - (, n) are formed in such a way that the increments of the unknowns at the i-th iteration are multiples of the degree base of the number system in which the device operates, and therefore ensured the absence of multiplication operations in (1) and (2)

0

five

0 0 5

0

five

0

five

. () 2 ,, i,

, B - thgg, -., U, i-,

In this way, ; corresponds to the value of the most significant bit

, (, j

The device works as follows.

With the pulse frequency at the sync input 4, inputs 1 are fed to the coefficients of the system of equations and free terms in the sequence shown in the table. In this case, the sequence of arrangement of the coefficients in the registers 7 of the nodes 6 and their transfers between the calculation blocks 3 is preserved.

After each pulse at synchronization input 5, inputs of the next system begin at inputs 1, and iterations at nodes 6 i-ro (, K) of calculating unit 3 begin iterations calculating i-e approximations of unknowns using relation (2). To do this, in each node 6 synchronous promotion of the coefficients of the system equations along the register pipeline 7 and supplying 18 digits of the corresponding unknowns via multiplexer 11 from the input is carried out. Through groups of elements, And 15 and 16 coefficients with corresponding signs are fed to the inputs of the adder 10, and to its other inputs through the elements And 17 of the group, partial sums from register 9 are passed. The result of the sum is written to register 9. The coefficients are transmitted through the multiplexer 12 through the pipeline to the output register 8 and then to the corresponding node 6 of the next (i + l) -ro calculation unit 3.

When a pulse appears at the input 5 of the synchronization iteration in blocks 3, the calculations are completed. The calculated cusps at each node 6 of the register 9 cusps are transmitted through the multiplexer 12 to the output register 8 with a left shift by one bit. Similarly, approximations of the unknowns are transmitted, which are formed as follows. Since the duration of the pulse at the synchronization input 5 is equal to three clock cycles of the synchronization input 4, then upon arrival at each node 6

The i-th block 3 of computation of the new pattern through the AND 14 element and the multiplexer 11 in the register 13 generates an increment of the unknown, which is in the next clock cycle, at the synchronization input 4, written through the element 14 into the free average unknown, transmitted from the previous block 3 (for the first block the unknowns are zero).

After P pulses at the sync input 4 in i-M (, K) block 3, the vector i-x of approximations of the solution of the P-th system of linear equations is calculated.

Thus, the delay in the computation of the vector of successive approximations of the unknown equation systems, as well as in the appearance of the solutions of the systems at inputs 2, is one clock cycle of the input 5 of synchronization.

Claims (2)

1. A device for solving systems of linear algebraic equations, containing k blocks of computations, where k is the number of iterations, from first to nth (where is the order of the system of linear algebraic equations), coefficients and free members of the system of equations connected to the information inputs from the first to the nth first block of calculations, respectively, from the first to the nth outputs of the device results connected to the outputs from the first to the nth k-ro block , computations, respectively, the outputs from the first to the nth i-ro computing unit (, ..., kl) are connected to the information from the first to the ng (i + l) -ro computing unit, respectively, characterized in that In order to increase the speed of the device, the first and second inputs of the device synchronization are connected to the first and second synchronization inputs of the first to kth computing units, respectively, each computing unit contains n operational nodes, in each computing unit jth (... , n) the information input is connected to the information input j-ro op istration node, the first and The second synchronization inputs are connected. here to the first and second inputs of synchronization of the operational nodes from the first to the fifth, respectively, jth output g 0 five 0 five 0 5 0 5 0 5 18 connected to the first output of the j-ro operational node, the second output of the 1st operational node (, ..., p-1) is connected to the control input of the (1 + 1) -th operational node, the second output (nth operational node k connected to the control input of the first operational node. 2. The device according to claim 1, characterized by the fact that each operational node contains (n-2) register, a register of a trace, an output register, the first and second multiplexers, an adder, the element And, from the first to the third group by m elements And each, where m is the variable size, the control input of the operational node is connected to the first information input of the first multiplexer, the information input of the operational node is connected to the first information input of the first register, the first synchronization input of the operational node is connected to the recording inputs ( register) from the first through (n + 2) th register of the viscous and output register, as well as to the first control inputs of the first and second multiplexers, the second synchronization input of the operation node is connected to the second control inputs of the first and second multiplexers, to the first input element I and-to the first inputs m of elements AND of the first group, the first output of the first register is connected to the second input of the element I, the output of which is connected to the second information input of the first multiplexer and the second information input of the first register a, the second output of which is connected to the information input of the second register, the output of the b-th register (where, ... n-1) is connected to the information input of the (b + 1) -th register, the output of the n-th register is connected to the information input ( n + 1) -th register and the first information input of the second multiplexer, the output of which is connected to the information input of the output register, the output of which is connected to the first output of the operational node, the output of the first multiplexer is connected to the information input of the (n + 2) -th register, whose output connected to the first inputs elements And, the second and . the third group, as well as the second output of the operational node, the first and 513942186 the second outputs of the (n + 1) -th register, whose approach is connected to the information input of the back-up register, the output of which is connected to the second one, is connected to the second inputs of elements of the second and third groups, respectively, of the output of the elements of the first, secondary input of the second multiplex - - - and the second inputs of elements AND of the first group. swarm and third groups are connected to the information inputs of the adder, you i rt-U2 2 n- i Э jn- i + j + 1 1 n-1 4n  eleven ajn ajj n ni-n  n n-5 a, n n-1 a fi n (Puz.2