SU781810A1 - Divider - Google Patents

Description

one

The invention relates to computing and can be used in analog-digital computing systems.

A digital device is known for dividing numbers entering a device with a parallel code, containing u {{framing units} implementing memorization, addition, shifting, etc. 1.

The disadvantage of the device is the large hardware costs for the organization of the communication channel between the digital blocks.

The closest to the present invention is a separating device, which makes it possible to calculate one-bit increments of the quotient when entering at its input single-bit increments of the dividend and the divisor, which allows, compared to digital devices for dividing numbers entering the device by a parallel code, to reduce costs equipment for organizing communication channels with other similar devices, i.e. simplify system communication. For example, a computational structure with an integral part of a known device allows parallelizing the computation process, which makes it possible to build sufficiently high-performance problem-oriented processors 2.

In the known device, the division process is based on the differential calculus formula.

.-Ai ",

where 2. private;

dx is the increment of the private; - divider; ) - increment the divider;

W - divisible;

DX is the increment of the dividend, while the exact formula of differential calculus

dx z-av

However, due to the dropping of the value of uit U V and it, there is an accumulation of error in the course of calculations.

The aim of the invention is to improve the accuracy of calculations. 3 The goal is achieved by the fact that a separating device containing a divider counter, a private counter, a unit for multiplying the increment-by-increment unit and an accumulator, the input of which is connected to the output of the unit of multiplying the unit by increment, is introduced a delay element, a switch, two OR elements, a counter of the highest order rows of the nets, a shaper of unit increments of the quotient, with the input of the delay element connected to the input of unit increments of the divider of the dividing device, the output of the delay element with It is connected to the input of the splitter counter and one of the inputs of the first OR element, the other input of which is connected to the input of the quotient counter, and the output is connected to the first input of the unit by a multiplier of a unit increment, the switch inputs are connected to the outputs of the divider and private counter, respectively, and the output connected to the second input of the unit of multiplying the value by a single increment, the output of the accumulating adder is connected to one of the inputs of the second OR element, the other input of which is connected to the input of the unit increments of the dividend The device is connected to the output of the second element OR, one input of the quotient unit is connected with the sign bit of the high digit discharges, the other input is connected to the output of the sign digit of the divider counter, the output of the unit increments private connected to the entrance of the private counter. The drawing shows a block diagram of a dividing device. The device consists of a counter 1 private, a counter 2 divisor, a switch 3, a unit 4 multiplying the magnitude by a unit increment of accumulating adder 5, a counter 6 of the highest discharge bits, a generator 7 unit increment of the particular, the first element OR 8, the second element OR 9, the element 10 delays. The input of the delay element 10 is connected to the input of 11 unit increments of the divider. The input of the counter 2 divider is connected t by the output of the element 10 delay. The input of the private counter 1 is connected to the output of a single increment generator of the private one. One input of the first element OR 8 is connected to the output of the delay element 10, and the other is connected to the output of a unit 7 increment of the quotient. One input of the switch is connected to the output of the counter 2 divider, and the other input is connected to the output of the counter 1 private. One input of unit 4 multiplying the value per unit is connected to the output of the first element OR 8, and the other input is connected to you 0 by the switch 3 run. The input of the accumulator 5 is connected to the output of unit 4 multiplying the value by one increment. One input of the second element OR 9 is connected to the input of 12 unit increments of the dividend, and the other with the output of overflows accumulating adder 5. The input of the counter 6 high-order discharges is connected to the output of the second element OR 9. One input of the individual unit increment maker is connected with a sign the house of the counter is 6 high-resolution bits, and the other is connected to the significant digit of the counter divider. The device multiplies according to the following system of equations it) /..s, (jn.) CK) (k -.) (K -.;. (K,; (,.,; (3)). Xk), ,. (k) The device works as follows: Before the start of the calculation, the counters and the accumulating adder are set to the zero state. After that, the device’s input receives the increments of the dividend and the divider and produces a single increment of the partial. Preparing the device for incrementing the single increment of the partial is done in one a cycle which is executed in two cycles. mules (I), (2) and (3). At the output of a unit increment generator 7 unit, a single increment of partial AX appears, the data e; w of which is calculated for the previous cycle, its sign is positive, if the signs of g Y are the same, and negative if the signs are different. The unit increment of the dividend enters through the second element OR 9 to the input of the counter for the high-order bits, and in the counter for the high-order bits and for the accumulating adder the value is generated. The unit increment Dg is fed to the input of the first element OR 8 and at the entrance account ika private, where the value is generated and output from the first or the element 8 single increment D1 to the input unit 4 for multiplying the values of e; ishichnoe incremented. To another entrance

Block 4 multiply

values 1 1 and a single priR1G1Snie from switch 3

enters great and

on dou, and on the output of this block the value is formed

d-scjne - U.jnv,).

-e The value obtained is fed to the input of the accumulating adder 5, and in the accumulating summator 5 and the high-order counter of fixture 6, the quantity is generated. e (-)) (k-1) .., (k-1). SC hviC After the termination of the transient processes in accumulator adder 5 and counter 6 of the highest bit, the second clock begins. In the second cycle, formulas (4) and (5) are realized. From the output of the delay element 10, a single increment of the AV divider is fed to the input of the counter 2 of the divider, where it is formed ...) In addition, through the first element OR 8, a single increment is fed to the input of the unit 4 multiplying the value by a single increment. The partial f from the private counter 1 goes through the switch 3 to the input of the unit 4 multiplying the value by a single increment, from the output of which the value D arrives at the input of the accumulating adder 5. In the accumulating adder 5 and in the counter of the 6th highest times, the value of g is generated (KL (K) tK) (K) The quotient is found when the unit increment of the divisor, the divisible and the quotient after each cycle changes sign, i.e. when a value is stored in the divider counter, equal to the specified divider value or less by a single increment, the found private value is stored in the private counter, and the trace 4 changes sign after each cycle. The algebraic sum of the increments issued from the unit increment of the quotient, equal to the sought quotient of the quotient, is output to another device. The device makes it possible to obtain a quotient without accumulating an error as it is calculated. The use of the device is advisable for building block computing structures.

Claims (2)

with a long time of continuous simulation of the process, where with a large number of iterations there should be no accumulation of error. Claims of the invention: A separating device containing a divider counter, a private counter, a unit for multiplying a unit increment and an accumulating adder, whose input is connected to the OUTPUT of a multiplier unit; one unit increment, characterized in that, in order to improve accuracy, an element is entered into it delays, a switch, two OR elements, a higher-order bit counter, a shaper of individual increments of a quotient, with the input of the delay element connected to the input of a single incremental divider of the dividing device In this case, the output of the delay element is connected to the input of the divider counter and one of the inputs of the first OR element, the other input of which is connected to the input of the quotient counter and the output is connected to the first input of the multiplication unit by one increment, the switch inputs are connected to the outputs of the divider and quotient counters, and the output is connected to the second input of the unit of multiplying the value by a single increment, the output of the accumulating adder is connected to one of the inputs of the second OR element, the other input of which is connected to the input of the individual drives The increments of the delimiting divider, the input of the high-order bit counter is connected to the output of the second element OR, one input of the quotient single increment generator is connected with the sign bit of the high-resolution bit counter, the other input is connected to the output of the sign bit divider counter, the output of the framer unit increments of the quotient is connected to the input of the quotient quotient. Sources of information taken into account during the examination 1. USSR author's certificate N 549808, l. G 06 F 7/50, 1975. 2.Neslukhovsky KS Digital differential; , analyzers. M., Mechanical Engineering, 1968, p. 92-94, fig. 28 (prototype). “R 41 -Jn