SU1390781A1 - Digital filter - Google Patents

Abstract

The invention relates to communication technology and remote control of automation devices. The purpose of the invention is to increase the reliability of the filtration result. First contains a driver (F) 1 pulses, a frequency divider (DF) 2, made in the form of an n-bit binary counter, DF 3, made in the form of an i-bit binary counter, And 4, 5. We are emails OR 6 and 7. Informats. the signal through F 1 arrives at the DCh 2 counting input, the clock Zal1 / s / (7m 7gg / s / 77. arrives impulses from the CM 6, gating the calculation of the pulses of the information signal for the clock of the clock pulse, el -t And 4 decrypts the minimum value of the number of pulses on DF 2 for the measuring interval corresponding to the lower boundary of the passband of the phytra. If the frequency of the input signal is higher than the lower limit of the passband, then from the elec tive And 4 a pulse is sent to the counting input of DF 3. DF 3 counts the number of received pulses during the received time. analysis, which is determined by the duration of the pulse arriving at the filter start input.Al-5 decrypts the max, the value of the number of pulses received at the PM 2, If the frequency of the input signal during the analysis time exceeds the upper limit frequency of the passband, an output appears at the output of the AND 5, dropping the DF 3 to zero 1 ill. with S (L SAE L O SH)

Description

The invention relates to communication technology and remote control of automation devices and can be used to allocate an information signal in a given frequency band.

The purpose of the invention is to increase the reliability of the filtration result.

The drawing shows a structural electrical circuit of a digital filter.

The digital filter contains the shaper 1 pulses, the first divider 2 Frequencies, made in the form of an n-bit binary counter, the second divider 3 frequencies, made in the form of an i-bit binary counter, the first 4 and the second 5 elements And , first 6 and second 7 elements of I.PI

The digital filter works as follows.

The information signal of a pulse or sinusoidal voltage from the input of a digital filter through the shaper 1 is fed to the counting input of the first divider 2, made in the form of a 1P-bit binary counter, to the reset input of which clock pulses come from the output of the first element OR 6, gating miscalculation of the pulses of the information signal for the duration of a clock pulse Cyj.

During the time of the first divider 2, the binary code of the number of pulses of the signal N is fixed:

.-one-.

from / and

(one)

where K is the coefficient, which takes into account

asynchronous clock and I-pulse;

fp is the frequency of the input signal;

The first element And 4 decrypts the minimum value of the number of pulses mmn the first divider 2 for the measuring interval corresponding to the lower limit of the passband of the digital filter.

If the frequency of the input signal is higher than the lower limit of the digital filter's bandwidth, then from the output of the first element I 4 a pulse is sent to the counting input of the second divider 3, which is made in the w / w of a 1-bit binary counter.

The second divider 3 counts the number of incoming pulses m during the received analysis time T, which is determined by the duration of the pulse arriving at the input trigger of the digital filter.

The second element And 5 decrypts the maximum value of the number of pulses received on the first divider 2 for the measuring interval 1 corresponding to the upper

 Z / L

bandwidth limit of the digital filter, N,: 2.

 The cop

If the frequency of the input signal during the analysis time T has exceeded the upper limit frequency of the passband, then a pulse appears at the output of the second element AND 5, which, through the second element OR 7, resets the second divider 3 to zero.

The analysis time T of the input signal is determined by the number of bits of the second divider 3. So, if the duration of the quantum miscalculation of the number of pulses corresponds to the duty cycle of clock pulses Q, then when calculating m quanta at the output of the i-th bit of the second divider 3, arrive at the output of the digital filter, with the value of the analysis time

. (d - with „-„, „(d-1), (2)

where

To set the digital filter to the initial state, the start signal outputs the first 6 and second 7 elements OR are connected to the reset inputs of the first 2 and second 3 dividers.

Thus, the proposed digital filter ensures reliable testing of the input signal in a given bandwidth during a time base with a relatively simple circuit implementation of the device, and the number of bits of the first 2 and second 3 dividers n and i is selected from relations (1) and ( 2) respectively.

Claims (1)

Invention Formula A digital filter containing a pulse shaper, whose input is a digital filter input, a first frequency divider, made in the form of an n-bit binary counter, the counting input of which is connected to the output of the pulse shaper, a second frequency divider, made in the form of an i-bit binary counter, the first and second elements And, that is. In order to increase the reliability of the filtering result, the first and second OR elements are introduced, the first inputs of which are combined and are the start input of a digital filter, the clock input of which is the second input of the first OR element, whose output is connected to the reset input of the first frequency divider, and the output outputs Dov first frequency divider connected to the corresponding inputs of the first and second elements AND, the output of the first of which is connected to the counting input of the second frequency divider, the output of the second element AND is connected to the second input of the second OR element, the output of which is connected to the reset input of the second frequency divider whose output is the output of the digital filter .