SU504306A1 - A device for generating clock signals - Google Patents

Description

one

: The invention relates to the technique of transferring discrete data and can be used for synchronization in systems for the transmission and reception of discrete code messages

A device for generating clock signals is known, comprising a first trigger, the outputs of which are connected to the first inputs of the first and second elements AND, the generator of reference pulses is connected to the second input of the last, and the output of the second element AND is connected through the first counter to one short-circuit input of the first element OR, another input of the latter is connected to the output of the third element And, to the first input of which through the inverter and the fourth element And connected to the second input of the third element And, connected to the second input of the first counter ka and one of the inputs of the second element OR, whose input through the first zadar line;: ski connected to the corresponding input of the first counter, the second delay line and the counter is connected to the input of an adder connected to the corresponding input of the first counter, the output of the first element OR is connected to the corresponding to the input of the second element OR and to the input of the change of the code in the additional first counter, as well as the second counter, trigger, fifth element And the decoder.

However, the known device has limited functionality. The aim of the invention is to expand the functionality of the device.

To do this, the input of the third AND element is connected to the input of the first trigger through the first element AND, the output of the first OR element connected through the second trigger and the fifth element AND connected to to the generator of the reference pulses, to the counting input of the second counter, send the corresponding output of the first counter to the second input of the decoder.

The invention is illustrated in the drawings. Fig. 1 shows a structural electrical device; in fig. 2 time diagrams for his work. A device for generating a clock signal contains a trigger 1, the outputs of which are connected to the first inputs of the element AND 2 and the element 3, the second input of the latter is connected to the generator of reference pulses 4, -a output through the counter 3 to one of the inputs of the element OR 6, to another the input of which is connected to the output of the element 7, to the first input of which through the inverter 8 and the element 9, connected to the second input of the element 7, is connected the second input of the counter 5 and one of the inputs of the element 10, whose output through the delay line 11 connected to according to The common input of counter 5, delay line 12 and counter 5 is connected to the input of adder 13 connected to the corresponding input of counter 5, and the second input OR 10 is connected to the output of the element OR 6 and to the input of code change to the additional counter 5, as well as the counter 14, the input of which is connected to the output of the element OR 6, which, in turn, is connected via the trigger 15 and the element AND 16 connected to the generator of the reference pulses 4, to the counting input of the counter 14, and the decoder 17, the first input of which is connected to the output of the counter 14, the second entrance - to the corresponding output of the counter 5 and the output to the first input of AND gate 7 whose second input via the AND gate 2 is connected to the input of flip-flop 1. The apparatus operates as follows. The first input pulse (see Fig. 2, a) overturns the trigger 1, which opens the elements And 2 and 3. At the same time, the counter 5 begins to accumulate the pulses of the generator 4 (see fig, 2, b). The second input pulse in turn passes through the element AND 7, which is opened by high potential from the output of the decryphragor 17 (see Fig. 2, e), and through the element OR 6 passes to the output of the device (see Fig. 2, c). This output impulse also overturns the trigger 15, sets the counter 14B to its initial state (see Fig. 2, d), goes to the OR 10 element and to the input of the code change to the additional counter 5.

The output signal of the element OR 10, delayed by the delay lines 11 and 12, transfers the code of the counter 5 to the adder 13 (see Fig. 2, d) from cyMvi-aTOpa 13 to the counter 5 (see Fig. 2, b).

Thus, after the first period of the input signal in the counter 5, a code is set equal to the difference of the counter and additionally to the code:; 0 | 41out. In the second period of the input signal, the counter is 5 days long.

Claims (1)

The output of the third element is And, to the first input of which through the inverter and the fourth element And, connected to the second input of the third element And, the second input of the first counter and one of the inputs of the second element OR, the output of which through the first delay line connected to the corresponding; the input of the first counter, the second line of the Delay and the counter is connected to the input c: at the tmator, from the second with the second, counts the number of incoming reference pulses (see Fig. 2, b), and the counter 14 subtracts them. When the maximum code value is reached in the counter 5, a pulse is generated, which is fed through the element OR 6 to the output of the device (see Fig. 2, c). The third in order input pulse does not pass through the element And 7, closed by the low potential of the decoder 17, which is in such a state until the counter codes 5 and 14 have converged (see Figures 2, b, d, e). The same third pulse passes through the element AND 9, the output signal of which changes the sign of the counter code 5 and through the element OR 10 produces a delay line 11 and 12. The metering of the counter code 5 with the code of the adder 13 and the transfer of the code of the adder 13 to the counter 5. Thus, the code of the counter 5 is adjusted to the code corresponding to the value of the input signal period. Next, the device operates as described above. When input pulses fall out, for example, at moments of time -t 2. output clocks are generated according to the code accumulated by adder 13 prior to the occurrence. The device provides work with clock signals, the repetition period of KOCHX varies within the capacity of the counters 5 and 14. At the same time, the adjustment to the hour of the beginning of the session takes only one period. After an accidental failure in the device, proper operation is restored already after the input pulse sequence following the failure. The invention The device for generating clock signals, containing the first trigger, the outputs of which are connected to the first inputs of the first and second elements AND, a generator of reference pulses are connected to the second input of the last, and the output of the second element AND is connected to one of the inputs of the first element OR, to the other input of the last one, by the input of the first counter, the output of the first element OR connect to the corresponding input of the second element OR and to the input of the code change in addition the first counter, as well as the second counter, trigger, fifth element AND, and characterized in that, in order to expand the functionality of the device, the input of the third element AND through which the second input through the second counter is connected to the input of the first trigger through the first AND element and a pesherator connecting the output of the first element OR, connected, in turn, 5 I through the second trigger and the fifth element AND, {connected to the generator of the reference pulses, to the counting input of the second count of the sensor, and to the second 1 input of the decoder corresponding Current output of the first 10 counters. Ljt.1  "/ ItI 1 © I  H. 1