SU1385119A1 - Time check signal selector - Google Patents

Abstract

The invention relates to selectors of time verification signals. The purpose of the invention is to reduce the likelihood of a false triggering of the selector, which contains detector 1, the EXCLUSIVE OR.2 element, 3 pulse generator, output device 4, pulse counter 5, delay elements 6 and 11, trigger 7, front driver 8, counter 9, device 10 comparison and pulse failure counter 12. Introducing new elements and forming new connections between the elements of the device allows the selector to react to the signal at the moment of its arrival. The accuracy of the binding to the exact time is determined only by the time the signal passes from the transmitting station to the receiving station, but the likelihood of a false selector triggering decreases. In order to expand the functions of the device, it is equipped with a counter 12 pulse failures, which allow one or several test signals to be delayed to trigger the trigger 7, which tilts the generator 3 and the counter 5, 2 or less. (L

Description

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This invention relates to time selector signal selectors for stand-alone devices and electric-clock systems.

The purpose of the invention is to reduce the likelihood of a false trigger of the time check signal selector.

FIG. I is a diagram of a time check signal selector; on 2 - time diagrams.

The time check signal selector contains detector I, an EXCLUSIVE OR 2 element, a 3-pulse generator, an output device 4, a pulse counter 5, a first delay element 6, a trigger, a front driver 8, a binary counter 9, a comparison device 10, a second delay element 11 and a counter 12 pulse failures.

In the proposed detector selector. is connected by the input of the logical circuit SPARK CHAKNTSEE OR 2, consisting of elements of the wooh NOT and three I. With the second input. the EXCLUSIVE OR circuit is connected to the output of the generator of 3 pulses simulating a time check signal coming from the detector (pulse duration and following period.). The second output of the generator 3 pulses is connected to the Binary counter 9, the second input of which through the And delay element receives the leading edge of the output signals formed by the front driver 8. The same output of the front driver 8. is connected to the strobe input of the comparison device 10 to the information input of which outputs are received, for example, from 1 through 8 bits, from the binary counter 9 ... The output of the comparison device is connected to detector 1, output which is connected to one of the inputs of the trigger 7, the output of which is connected to the inputs of the installation of the generator 3 and the pulse counter 5, and the second input through the first delay element 6 is connected to the output of the EXCLUSIVE OR circuit. The information input of the counter 5 pulses is connected to the output of the generator 3, and the output to the input of the output device 4, which forms the output pulse of the selector.

When a trailing edge of the time verification signal arrives at the input of the shaper 8 (six pulses with a duration of 100 ms with a filling frequency of 1 kHz), a sine-like shape often occurs in it

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you fill the impulses in the right arc. This means that only the falling edge is separated from them, which is fed to the sampling input of the comparator device 10 and through the input delay element 1I. Installation O of the binary counter 9, the counting input of which receives the frequency (for example, 100 kHz) from the 3-pulse generator. From the binary counter, from the outputs (for example, the first eight) bits of information enters the comparison device, where the number is coded 100. If at the moment of the falling edge the number 100 in binary code appears at the output of the comparison device, then signal input to the detector. Any other number that is present at the input at the moment when the trailing edge arrives does not give an output signal. Therefore, the detector 1 receives the SI1-signals only with the filling frequency G fp F, where Gd is the expected firing frequency; F - clock frequency.

Thus, to the detector input. 1, only the expected pulse rate is received. In this scheme, the selector reacts to the signal practically at the moment of its arrival and the exact time reference is determined only by the time the signal passes from the transmitting station to the receiving station, but the probability of a false selector triggering is sharply reduced.

From detector 1, the signal simultaneously arrives at the circuit EXCLUSIVE OR 2 and. trigger 7, which removes the signal from the input Setting O of the pulse generator 3 and pulse counter 5. At the output of generator 3, signals begin to form, similar to the time test signals, with an accuracy of the reference frequency supplied to generator 3. At both inputs of the EXCLUSIVE OR 2, the reference begins the signal from the generator and the one being investigated from the detector, with the full coincidence of both signals at the output of the EXCLUSIVE OR circuit, there is no signal, Trigger 7 remains in the state in which generator 3 and counter 5 remain in operation mode. In this case, pulses of the reference frequency are recorded in counter 5.

analogous to the pulses of exact time ,,

As soon as the signal coming from detector 1 to the EXCLUSIVE OR 2 circuit becomes different from the reference one, a signal is generated at its output, which, through the first delay element 6, sets the trigger 7 to its initial state at which the generator 3 and the counter 5 zero and the entire circuit returns to its original state. When the input signal coincides with the reference one, 6 signals are recorded in the counter 5, and with the leading edge of the 6th signal, the output device 4 receives a correction signal, which is the output signal of the selector. In order to expand the functionality of the selector, it is equipped with a pulse failure counter 12, which allows one or several test signals to trigger the trigger that oscillates generator 3 and counter 5, at the time of receiving signals. This increases the likelihood of receiving time verification signals,

Formula of Invention

The selector of time verification signals containing the detector, the output of the cells is not

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Compiled by M.Haustov Editor L, Pcholinska Tehred M.Hodanich Proofreader 0, Kundrik

Order 1413/45

Circulation 373

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab ,, d, 4/5

united with the first input of the EXCLUSIVE OR element and with the first trigger input, the output of which is connected to the inputs Installation of the pulse generator and pulse counter, the output of the pulse generator is connected via a pulse counter with the input of the original device and directly with the second input of the EXCLUSIVE OR element, output connected to the input The first delay element, characterized in that, in order to increase the reliability of operation, it is equipped with a falling front driver, a binary counter, a comparison device, a second element m delay, as well as a pulse failure counter, the output of the comparison device is connected to the detector input, the information input is connected to the output of a binary counter, the counting input of which is connected to the output of the pulse generator, and the INPUT setting O is connected to the rear edge of the second , to which the strobe device of the comparison device is connected, the output of the first delay element is connected to the input of the pulse failure counter, the output of which is connected to the second input of the trigger, and the input Installation O to the silo ode trigger.

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Claims (1)

A time verification signal selector containing a detector with an output that is connected to the first input of the EXCLUSIVE OR element and the first input of the trigger, the output of which is connected to the inputs. Setting 0 is a pulse generator and a pulse counter, the output of a pulse generator is connected via a pulse counter to the input of the output device and directly— MORE OR, by the output of the first delay element connected to the input, characterized in that, in order to increase the reliability of operation, it is equipped with a trailing edge shaper, a binary counter, a comparison device, a second delay element, and a pulse failure counter, the output of the comparison device being connected with the detector input, the information input - with the output of the binary counter, the counting input of which is connected to the output of the pulse generator, and the input - Setting 0 through the second delay element is connected to the output of the rear shaper Ronto one connected to the gating input of the comparator, an output of first delay element is coupled to the input of the pulse counter of failures, the output of which is connected to the second input of the flip-flop, and the input setting of 0 - to the output of the flip-flop.