SU1383500A1 - Analog-to-digital parallel-series converter - Google Patents

Abstract

The invention relates to the field of measurement technology and can be used in the construction of high-speed information transducers in broadband signal processing systems. Into a device containing a p-bit parallel analog-to-digital converter 7, comparators 2, differential voltage drivers 4, a 1-source signal and an encoder 8, in order to improve the accuracy and speed of the conversion by implementing both amplitude convolution of the signal and signal combining into moments of equality of voltages at the input and output of switching elements, introduced analog inverters 5, keys 6, first and second groups 9 and 13 elements EXCLUSIVE OR, shapers 10 and 11 logical units and zero, respectively State and the element OR 12. 2 Il. (L from 00 00 ate

Description

The image is related to software measures and can be used by Juvano in building the speed of the Dp-ix information converters in the systems for processing wideband signals.

The aim of the invention is to improve the accuracy and speed of the transformation due to the implementation of the amplification convolution of sigigs at the moments of Equivalence of voltages at the input of the switching elements.

1 FIG. 1 shows the structured 4th device; in fig. 2 - dia paMMa of his work.

: The converter contains a source - 1 reference signal, (2 -1) com- ijiapaTopoB 2, input bus 3, 2 formers 4 of differential voltage -; eni, -1 analog inverters 5, 2 keys 6, parallel analog-digital converter 1, “ Shfrator 8, the first group 9 of 2 Elements EXCLUSIVE SHSh, shaper 10 logical zero, shaper 11 logical units, the element SHSh 12, the second group 13 of the n Elements EXCLUSIVE SHS.

The operation of the parallel-to-serial analog-to-digital-13OH converter with linearly operation; the input signal is illustrated in the 15TCW (Fig. 2). The entire range of possible changes in the input signal, | is defined as p 2 (where ha is the number of upper digits of the output binary code, and p is the conversion coefficient of the considered ADC), divided into the diagonal values corresponding to the unit of discreteness of the higher digits of the p. The unit of discreteness of the higher bits of the output code is associated with the unit of discreteness of the small-sized parallel ADC 7 by the following relation, where n is the number of bits of the parallel ADC 7 (the number of low-order bits), q is the unit of discreteness of the parallel ADC 7. The range is pre Parallel ADC is defined as q (2 -1).

At the output of the reference signal source, reference voltages are formed, corresponding to the levels p, 2p, 3p.

2p. In this case, the voltage with the levels of p, 2p, .... () p are supplied respectively to the inputs of the comparators from the first to (2th), and the voltages with even levels

,

2 p are respectively fed to the differential voltage shapers from the first .i (go 2 - i.

If the input signal does not exceed the voltage corresponding to level p, then logical O are set up at the outputs of the Comparators. At the output of the first element EXCLUSIVE W of group 9, logical 1 is formed. The first key is opened and all other keys are in the closed state. The input signal goes directly to

the input of the parallel ADC 7. The output code through the elements EXCLUSIVE OR of the second group 13, which perform the role of controlled inverters, without -in- verti comes to the output,

Forms and junior categories. At the output of the encoder 8, a zero value is formed in the m most significant bits.

When the input signal exceeds the level, the first comparator is triggered. As a result, the first key is closed, and the second key is opened. To the input of the parallel ADC 7, the differential voltage 2p-iv is supplied from the first differential-voltage generator,

(section 2 of FIG. 2). This voltage is converted to a code that is fed from the output of the parallel ADC 7. inputs of EXCLUSIVE SHS elements of the second group 13. The first inputs of the elements of the EXTREME OR OF the second group 13 receive a logical 1 signal from the output of the OR 12 element, which inverts the vertical code of the parallel ADC 7. At the output of the encoder 8, a unit is formed in the lowest m among the senior output bits, code.

When the input voltage exceeds the value of 2p, the first and second comparators operate. At the exit of tre-. In the second element of the EXCLUSIVE OR group 9, a control signal is generated that opens the third key. As a result, the voltage from the output of the first analog inverter, defined as (2p-Ug.), Goes to the input-to-parallel ADC 7.

At the output of the second element of the EXCLUSIVE SHW group, a logical O is formed, since the first and second comparators operate. At the same time, a control signal is inserted through the SHSh 13 element, which ensures the passage of the direct code from the output of the parallel ADC 7 to the formation of a n young

our discharges At the output of the encoder 8, a unit is formed in the second bit.

Similarly, the device operates with an increase in the input signal at subsequent sites, i.e. the amplitude convolution of the signal at the input of the parallel ADC 7 is realized. At the same time, the need to convert the output code into the Gre code, and then into the binary code, which occurs in the known series-parallel analog-digital converters, is no longer necessary.

Claims (1)

Formula of gain Parallel-to-serial analog-to-digital converter containing a n-bit parallel analog-to-digital converter, where n is the number of low-bits-output binary code, (2 -1) comparators, where m is the number of high-order bits of the output binary code, 2 differential voltage drivers, the first inputs of the comparators are combined with the first inputs of the differential voltage drivers and are the input bus, the second inputs of the comparators are connected to the corresponding first outputs of the reference signal source, and The comparators are connected to the corresponding inputs of the encoder, the outputs of which are the output bus of the higher bits, the second outputs of the reference signal source are connected to the second inputs of the corresponding differential voltage former, in order to increase the accuracy and speed of the conversion by implementing amplitude convolution signal, it entered 2 keys, forming poRjrejfb logical zero, the formative unit of logic, -1 analog inverters, the first and second groups of 2 and II elements EXCLUDE - SCHI And, accordingly, I.PI element, while the outputs of the keys are combined and connected to the input of a parallel analog-digital the converter, the information input of the first key is the input bus, the information inputs of the even keys are connected to the outputs of the corresponding differential voltage generators from the first to the 2nd, and the information inputs of the match keys, except the first, are connected to the output the first analogue inverters from the first to the –ljth, whose inputs are connected to the outputs of the differential voltage drivers of the same name, the control inputs of the keys are connected to the outputs of the corresponding elements EXCLUSIVE OR of the first group, the first input of the 2nd group EXCLUSIVE OR of the first group is connected to the output shaper logical zero, and the output of the i-ro comparator, where, 2, ... (2-1) is connected to the first input of the i-ro and the second input of the (1 + 1) -th element EXCLUSIVE SHS of the first group, the second input of the first element EXCLUSIVE OR first g The unit is connected to the output of the logic unit shaper, the outputs of the even-numbered elements of the EXCLUSIVE ISH1 of the first group are connected to the corresponding inputs of the OR element, whose output is connected to the first inputs of the EXCLUSIVE OR elements of the second group, the second inputs of which are connected to the corresponding outputs of the parallel analog-digital converter, and the outputs corresponding to the lower-order output bus. / T) p  P P X rtopqA LC / 7 Participation,