SU1383343A1 - Device for computing function a raised to power m - Google Patents

Description

(21) 4128950 / 24-24

(22) 03.10.86

(46) 03/23/88. Bul №11 (72) E.Ya.Vavruk, A.A.Melnik and I.G. Tsmots

(53) 681.325 (088.8)

(56). USSR author's certificate №752334, cl. G 06 F 7/552, 1980.

USSR Author's Certificate No. 1087990, C. 06 F 7/552, 1983.

(54) DEVICE FOR CALCULATION OF FUNK1DII A

(57) The invention relates to computing and can be used in high-performance digital information processing devices to calculate the function.

BUT . The purpose of the invention is to reduce

hardware costs. The essence of the invention is that in the proposed device in each computing unit an analysis of K-bits is performed, which makes it possible to reduce the number of computing blocks by K times. The device contains blocks 4.1-4. (2 -2) exponentiation (where K is the number of analyzed bits of the exponent in one computing unit), switch 5, L computing units 6

, (logira) + l-K

(L - ---- where K is the number

in the analyzed bits in the group, m is the exponent), each of which contains registers 7–9, switch 10, unit 11 for raising to the 2nd degree, multiplier 12. 1 sludge.

t

ate

00 00

with so

four:

with

eleven

The invention relates to computing and can be used in high-performance digital information processing devices to calculate the function A.

The purpose of the invention is to reduce hardware costs.

The drawing shows the functional diagram of the device.

The diagram shows the clock

input 1, input 2 of the exponent and input 3 of the base of the degree of the device, blocks 4, - 4 to the erection of

degree (where K is the number of analyzed degree index bits in one computing unit), switch 5, L computing blocks 6, each of which contains a register 7 degree indicators, registers 8, -, a correction factor, result register 9, a switch 10 , construction block 11

2nd degree, multiplier 12, input logical unit of the device, output

14 devices. I. .

The proposed device uses an algorithm for raising the number A to the gth degree, in which the exponent is divided into groups of K bits, with sequential analysis of the data of the groups from left to right and execution with the previous stump followed by multiplying it with a correction factor. For each group analyzed the correction the multiplier is equal to the result of raising the number A to a power equal to the number written in this group. When analyzing the first group, the previous result is assumed to be one.

The device works as follows.

The base of the degree from input 3 is passed to the inputs of blocks 4, - .. of a degree,

of this erection of the result in the 2nd stegda in each (i - 2) -M (i 1, 2, ..., 2) block 4, -. 2

it is raised to the (1-1) th degree. Higher K bits of the exponent from input 2 arrive at the control input of switch 5 and switch it so that, at zero, the control input returns to the output information from the first input, at one, the information from the second input, etc. .

eight

0

In the first clock in registers 7,8 ,, 8 ,. . ,, and 9 of the first extremity block 6, information is recorded, and registers 7 and 9 are recorded, respectively, the exponent without K of the higher bits and information from the output of switch 5 (correction factor a into registers 8, 82, ... ,., j - the basis of the degree and information from the outputs of blocks 4,, 42, ..., raising to a power.

In the first computing unit 6,

15 the information from the output of register 9 (the previous result) at block 11 is raised to the 2nd degree and is fed to the input of the multiplier 12, where it is multiplied by the information from the output of switch 10 (correction factor). The information from K to the upper bits of the register 7 controls the switching of the switch 10 so that, at zero, the control input receives information from the first input at one output, information from the second input at one, and so on. The result of the multiplication from the output of multiplier 12 is fed to the input of register 9 of the second computational block 6 ...

In the second cycle, information is rewritten from the outputs of the first computing unit 6, to the second computing unit 6. One

in the first computational

new elements of the array. In block 6.

temporarily

block 6, recorded

You are processing a rum computing unit 6 information from the output of register 9, pass

0 through the raising unit 11, being raised to the 2nd degree and arriving at the input of the multiplier 12, where it is multiplied by the information from the output of the switch 10. The information at the output of the com-.

5, the mutator 10 is set to the high register bits 7.

After the last clock cycles, the device works in a similar way, i.e. in each computing unit 6 is performed

0 one iteration of exponentiation algorithm. Erection c. the degree is fulfilled when the operands of all computational units 6 pass through.

5 The device operates according to the conveyor principle. Its speed is determined by the execution time of one iteration, i.e. tact of the conveyor. This time is

T tg t,

where t is the time of recording information in

 register;

ti is the delay time of information on the exponential bb; t is the multiplication time.

Z

Claims (1)

Invention Formula A device for calculating function A, comprising a switch and L computing units (L (log2ra) + l-K ... v-, where K is the quantity TO analyzed bits c. group, m - exponent, each of which contains a correction multiplier register, (1-jK) - exponent register, result register, switch and 5 multiplier, the base input of the device degree connected to the input of the first register of the correction multiplier of the first computing unit , the result register of which is connected to the switch output, which is different in that, in order to reduce hardware costs, it contains (2-2) construction blocks in the 2nd degree and every computational  V the block additionally contains (2 -2) correction factor registers and a 2 nd degree raising unit, the base of the degree of the device being connected to the inputs of the 2 nd degree raising blocks and the first information input of the switch, the second information input of which is connected to the input of the logical unit of the device devices are connected to the control input of the device switch, output (i-2) -ro (, 2, ..., 2) the exponentiation unit is connected to the i-th information input of the switch and the input (i-l) -ro of the register of the correction multiplier of the first computational block, LlogjmJ-b 1-K lower-order bits of the device’s exponent are connected to the input of the exponent of the first computational unit, in each j-m (, 2, ..., b) -m the computing unit of the K-senior bits of the exponent of the exponent is connected to the control input of the block switch, the first information input of which is connected to the input of the logical unit of the device, the output (il) -ro of the correction multiplier register is connected to the i-th information input of the block switch, and the input (il) -ro of the correction multiplier register (j + l) -ro of the computing unit, the output of the switch of the block is connected to the first input of the multiplier, the output of the result register is connected to the input of the raising unit to the 2nd degree, the output of which connected to the second input of the multiplier, the output of which is connected to the input of the result register () -ro of the computing unit, vspod + l- (j + l) K junior the bits of the register of the exponent are connected to the input of the register of the exponent (j + l) -ro of the computing unit, the synchronous inputs of all the registers are connected to the clock input devices, the output of the multiplier L-ro. the computing unit is the output of the device.