SU1383337A1 - Device for computing functions using table method - Google Patents

Abstract

The invention relates to computing technology and can be used as an autonomous specialized calculator or as a functional expander as part of large computers. The aim of the invention is to improve the accuracy due to the use of quadratic approximation. The device contains the first memory block 1 of the approximation constants.

Description

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second block 2 of memory of constants of approximation, block 3 of summation, block 4 of output registers, first 5, second 6, third 7, fourth 8 registers of block 4 output registers, output 9 results, register 0 argument, 11 input 11 argument, first 12 , the second 13, the third 14, the fourth J5 G1) uppa of the elements OR, the multipliers 16-

18 high, middle, low byte, register 19 constants, control block 20, start input 21. The proposed device uses a quadratic approximation, which makes it possible to calculate the value of the function 5-10 times more precisely over a given interval of argument variation than with a linear approximation. 1 il.

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This invention relates to a computational technique and can be used as a specialized calculator.

The purpose of the invention is to improve the accuracy. Due to the use of quadratic approximation.

The drawing shows the functional diagram of the device.

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The device contains the first block J

memory approximation constants, the second block 2 memory approximation constants, block 3 summation, block 4 output registers, first 5, second 6, third 7, fourth 8 registers unit 4 output registers, outputs 9 result, register 10 argument input 11 argument, the first 12, the second 13, the third J4, the fourth J5 of the group of elements OR, the old byte multiplier 16, the average multiplier J7. 6afiTa, J8 low byte multiplier, constant register 19, control block 20, start input 21, first 22, second 23, third 24, fourth 25, fifth 26, sixth 27, seventh 28, eighth 29, ninth 30 , ten of the 31 outputs of the control unit, the output of the high-order 32 bits of the high byte, the output of the 33 high-order bits of the middle byte, the output of the 34 high-order bits of the low byte, the output of the 35 lower bits of the high byte multiplier, the output of the 36 low bits of the multiplier middle byte, output 37 low bits multiplier low byte, first adder 38 corrected amounts, the first intermediate cj MMaTop 39, the second intermediate adder 40, the second 41, the third 42, the fourth 43 adders of the corrected amounts, information outputs 44-47 of the first, second, third, fourth adders of the adjusted amounts, the fifth register 48, the sixth register 49 , the seventh register 50 of the block of output registers, one-half 51 and twelve 52 outputs of the control block.

The device operates in the following 1M manner.

The interval of change of the argument is divided into 2 sections (n is the highest order of the argument without a sign bit).

At each of the sections of the function, a second-order curve is approximated.

y Ah + Bh + C,

the coefficients of which are A, B and C are chosen based on the minimum value of the root-mean-square error using the least squares method.

Argument X, coefficients A, B and C and functions y are represented as K1-bit binary groups. In the particular case when the binary resolution of the argument x, coefficients A, B, C and the function is 24 binary bits, it is advisable to take n 7, K 3, 1 8.

The calculation of the function is performed according to the Horner scheme, i.e. computed

y (AH + B) x + C.

In the first clock cycle, the signal from the second output 23 of the control unit 20 controls a three-byte argument to the argument register 10, which has a left (senior) in the left (first) byte

the binary bit is significant, and the signals from the eleventh output 51 of the control unit 20 reset the registers from the first to the seventh 5-8.48-50 block of the output registers,

In the second cycle, the third (lower) byte of the constant A (a) is extracted from the first output 22 of the control unit 20 from the first block of memory of the approximation constant given by the higher-order bits X, and through the fourth group of elements OR it enters to the inputs of the second multipliers of multipliers J6-J8, to the inputs of the first factors of which the signal from the third 24 output of control block 20 from the register JO of the argument to the first, second and third groups of elements OR I receive g bytes of argument x: to the multiplier 16 high byte ( bytes x,), on multiplier 17 middle byte (byte x), multiplier 18 low byte (byte x,).

In the third clock cycle of the signal from the ninth 30 of the output of the control block 20, the operands a., And x are entered in the corresponding multipliers 16-18 of the high, middle and low byte.

In the fourth cycle, the signal from the tenth 31 output of the control block 20 results the multiplications, a ,, and, from the output of the multipliers 16-18 high, middle and low byte, the intermediate adders 39 and 40 and the adders 38, 41-43 interim amounts, i.e. The process of calculating the magnitude of x a begins.

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-x-aS x, S -a-S + x-S-ajS + + x, (c, .S- + als;) +

+ (c; s% a / S-). + (C; S H- a .S-),

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the outputs of the multiplier 16 high byte, the value of c 2 and aj at the outputs of the intelligent inhabitant 17 of the middle byte, the values of c and a, at the outputs of the multiplier J8 of the lower byte.

In the fifth cycle, the signal from the one-fifth 51 output of the control unit 20 controls the contents of the adders 38, 41-43, respectively, into the registers 5-8 of the unit 4, the output registers. This ends the cycle of multiplying the argument x by the low byte a.koe bycy A.

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the EFFICILE L, COEFFIDaley multiplies the argument X by the middle byte of the amplifier A and by the high byte of the sample A. This is performed in cycles, starting with the second one, in which from the first memory block 1 at the address specified by the higher bits x using the signals from the fourth 25, and then from the fifth 26 outputs of the control unit 20, extract the second (a) and first (b,) constant bytes of A.

After three cycles of multiplying x by A into are completed.

Five registers -6-8, 48-50 are six bytes of this work.

Then, the signal from the sixth output 27 of the control unit 20 at the address specified by the higher bits of the argument x, from the second block 2 of the constant memory, approximates the first, second, and third gates of the OR elements to the multipliers 16-J8 by the coefficients B: to the multiplier 16 high byte b, multiplier 17 middle byte b, and multiplier 18 low byte b. Simultaneously by the signal of the eighth output 29 of the control block 20 from the constant register J9

0 through the fourth group of elements OR to the inputs of the second multipliers of multipliers 16-18 enters a constant byte 1 of the form 00000001.

In the subsequent ie, two clocks, according to the signals from the ninth 30 and tenth 31 outputs of the control unit 20, the value B.1 is calculated in the multipliers 16-J8. As a result of the operation of the 3 pummators block, the value of Ax + B1 is formed at the outputs 45-47 of the block 3 of adders, at the output 44 of the block 3 of the adder there is zero.

Further, by the signal from the eleventh output 51 of control unit 20, the contents of adders 38, 41, 42 and 43 of summation unit 3 are entered into registers 5-8 of function register 4, and the contents of registers 48 and 49 are shifted to the right by one byte. As a result on

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The contents of registers 6-8 and 48 must be shifted two bytes to the right so that in register 50 there is a four byte of the value Ax + B. Such a shift in the device is performed by two cycles of multiplication by 0. This multiplication is performed by the signal of the eighth output 29 of the block 20 control.

This means that from the register 19 the constants to the inputs of the second multipliers of the multipliers LesS are given the byte of the consultant O of the form 00000000, while the inputs of the first multipliers of the multipliers are x.

According to signals from the ninth 30 and the tenth 31 outputs of the control unit 20 in multipliers 16-18, X is multiplied by O. Zeroes appear on their outputs, which are summed on adders 41-43 of the corrected sums with the contents of the first 5 second 6 and third The 7 registers by the signal from the eleventh output 51 of the control unit 20 allow shifting their contents one byte to the right by repeating such multiplication twice the registers of the block 4 output registers two bytes to the right. Since during these two cycles from the twelfth output 52 of the control unit 20, no signal is applied, the contents of the register 50 are not output.

In the next four cycles, when the twelfth signal is present 52, the argument x is multiplied by four bytes of the value Ax + B.l, i.e. calculation (Ax + B.1): X. After each multiplication cycle. (Ax + B. 1); - X () in the order of (Axi + Bl) Xs (Ax + B.1) X4 {Ax + + Bl) X, the contents of the registers of block 4 of the output registers are shifted by one byte to the right, as a result In subregistries 5-8, 48, and 50, there are seven old byte conducts (Ax + B.1) -X.

In the last cycle, the value of C ,, is added to the value (Ax + B.1) -X. This cycle is performed similarly to the cycle Ax + B ..

As a result, in the first register there are zero, and from the second to the seventh (6-8.48 and 50) corresponding bytes of the function y. Since the x argument and the A, B, and C coefficients are three-byte, the result can only be three-byte, because in bytes of the 48th, 6th, 49th, and seventh 50 registers there are inaccurate numbers. Therefore, the calculated value of the y function is removed from the second 6, the third 7, fourth 8 registers of block 4,

Claims (1)

Invention Formula A device for calculating functions in a tabular manner, containing 0 5 20 5 thirty about hp five the first and second memory blocks of the approximation constants, the summation unit, the multiplication unit and the control unit, the first, second and third outputs of the control unit are connected to the inputs of the higher address bits of the first memory block of the approximation constants, in order to improve the accuracy due to the application of quadratic approximation, the argument register, the output register block, the constant register, four groups of OR elements are added to it, the multiplication block contains the multiplier of the high byte of the argument, the mind the middle byte argument knob, the low byte multiplier of the argument, and the summation block contains two intermediate adders and four adders from the corrected sums, with the device argument input connected to the information inputs of the argument register, the high byte outputs of which are connected to the first memory block. The approximation constants and with the higher-order address bits of the second memory block of the approximation constant, the high, middle and low byte outputs of the argument register are connected to the first inputs of the OR, first, second, and third groups, the second inputs of which are connected to the high, middle, and the low bytes of the second memory block of the approximation constants, the outputs of the elements OR of the first, second and third groups are connected to the inputs of the first factors of the multipliers of the higher, middle and the low byte of the multiplication unit, the inputs of the second factors of which are united with the output of the OR elements of the fourth group, the first and second inputs of which are connected to the output of the first memory block of the constants of the approximation and the output of the constant register, respectively, the outputs of the higher bits of the high, middle and low bytes are connected with the inputs of the first addendum, respectively, of the first adder of the corrected sums, the first intermediate adder and the second intermediate adder-ra, the outputs of the lower digits of the multiplier th senior and middle byte are connected to the inputs of the second terms soot Respectively, the first and second intermediate adders, the outputs of which are connected to the inputs of the first addendum, respectively, of the second and third adders of the corrected sums, the input of the first addendum of the fourth adder, the corrected sums are connected to the low-order multiplier outputs of the second intermediate adder are connected to the transfer input the first intermediate adder, the transfer output of which is connected to the transfer input of the first adder of the corrected sums, the input of the second aemogo coupled to an output of the second adder transfer corrected amounts which transfer input connected to the output of transference third adder sums of corrected input of which is connected with the transfer. the transfer output of the fourth adder of the corrected amounts, the outputs of the adders of the corrected first to fourth sums are connected to the information inputs of the registers from the first to the fourth block of output registers, the outputs of the first to third registers of the output registers are connected to the inputs of the second component of the second, third and third respectively the fourth adders of the adjusted amounts, the outputs of the registers from the fourth to the sixth block of output registers are connected to the information inputs of registers, respectively, from the fifth to the seventh block of output registers, the outputs of the seventh register of the block of output registers are connected to the third inputs of the OR elements of the fourth group, the outputs of the registers from the second to the fourth block of output registers are outputs of the calculated function of the device, the trigger input of which is connected to by the same input of the control unit, the fourth and fifth outputs of which are respectively connected to the gating inputs of the entry and selection of the argument, the register of the argument, the sixth and the seventh outputs of the control unit are connected respectively to the low-order bits of the address of the second memory block of the approximation constants, the eighth output of the control block is connected to the input gate of the register assembly constant, the ninth and ten outputs of the control block are connected to the inputs of the corresponding gate. multiplying and resolving a sample of multipliers of the high, middle, low bytes, the eleventh output of the control block is connected to the clock inputs of the registers from the first to the seventh block of output registers The twelfth output of the control unit is connected to the gating input of the sample of the seventh register of the output register unit.