SU1381727A2 - Digital information receiver - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve noise immunity. The discrete information receiver contains analyzer 1 of the transmission phase transfer parcel 1, first valve 2, trigger 3, shift register 4, counter 5, adder 6, additional counter 7, interference level analyzer 8, signal level prediction unit 9, threshold unit 10. The goal is achieved by introducing the second and third valves 12, 13, the inverter 1 1, the subtraction unit 14 and the signal level analyzer 15. I Il.

Description

00

00

Yu

The invention relates to telecommunications and can be used in information transmission systems, including the use of automated controls.

The purpose of the invention is to improve noise immunity.

The drawing shows a structural electrical circuit of the proposed receiver.

The discrete information receiver contains analyzer I of the end of the transmission phase signal, first valve 2, trigger 3, shift register A, counter 5, adder 6, additional counter 7, interference level analyzer 8, signal level prediction unit 9, threshold unit 10, inverter II, the second valve 12, the third valve 13, the subtraction unit 14 and the signal level analyzer 15.

The receiver works as follows.

In block Y of the prediction of the signal level, the calculated value of the level of the intended information signal is laid. It is matched with the recorded signal level value obtained when the previous sequence was received.

The binary information signals, consisting of several identical blocks, with a preliminary phase-start signal, arrive at analyzer 1 at the end of the transmission phase signal and at the first, second and third valves 2.12 and 13.

After receiving the phase-start signal from the analyzer 1 of the end of the transmission phase signal, a pulse is triggered, setting trigger 3 to such a state that the first valve 2 opens and passes the following information. The trigger 3 through the inverter 11 shuts the second valve 12, which disconnects the analyzer 8 noise level from the input of the receiver. At the same time, by the signal from trigger 3 from the analyzer 8, the level of interference at the receiver input is in parallel supplied to the threshold unit 10 and the subtraction unit 14. In addition, the trigger 3 opens the third valve 13 and the voltage of the mixture of the signal and interference goes to the subtraction unit 14. Block 14, the subtraction, receiving a mixture of signal and interference and having recorded information about the level of interference received from the analyzer 8 level of interference, produces a selection of the level of the information signal.

The obtained information about the level of the information signal is fed to the signal level analyzer 15. Binary information from valve 2 is fed to shift register 4 and additional counter 7. After the first block of binary information is recorded, additional counter 7 outputs a pulse to shift register 4 and counter 5, with the block information from

register 4 goes to adder 6, and one is written to counter 5. From the analyzer 15, the signal level measurement results are fed to the signal level prediction block 9, where they are recorded for subsequent received signals.

At the same time, the signal level information determined by the first block of information passes through block 9

without changes and falls into the threshold block 10. In the threshold block 10, the real value of the signal-interference ratio is determined, which then goes to counter 5 and the signal i

Records the number and cpsgv signal repetition in the reception process.

After recording the next block of information, a deuce is recorded in counter 5, and in adder 6,

bitwise addition of ones and zeros. When the number of information reception cycles will coincide with the corrected number of cycles recorded in counter 5, the pulse from the counter output to the trigger 3 and the signal level analyzer 15 goes to the adder 6 and the resulting information passes to the receiver output. In addition, the same

a pulse arriving at trigger 3 and a signal level analyzer 15 prepares the discrete information receiver for further work. In block 9, for the next received signal, the corrected signal level is obtained by comparing the calculated level of the expected signal with the value obtained when receiving this sequence. Analyzer 8 performs further noise level analysis. All this allows you to set the value of cycles of repetition of information necessary for reliable reception

signals. As a result, it becomes possible to automatically optimize the time of receiving information during the process of receiving information itself, which increases receiver noise immunity and shortens reception time.

Formula of invention

Receiver of discrete information, according to autor. St. 663123, characterized in that, in order to improve noise immunity, a second valve, an inverter and a third valve connected in series, a subtraction unit and a signal level analyzer are inserted into it, the second input

the first valve is connected to the input of the noise level analyzer through the second valve, the first input of the third valve is combined with the analyzer input of the end of the transmission phase signal and is the input of the receiver of discrete information, the trigger output is connected to the second inputs of the level analyzer

interference and the third valve, as well as through the inverter - with the second input of the second valve, the output of the noise level analyzer is connected to the second input of the subtraction unit, the output of the counter

connected to the second input of the signal level analyzer, the output of which is connected to the input of the signal level prediction block.

Claims (1)

Claim The discrete information receiver, according to autosw. No. 663123, characterized in that, in order to increase noise immunity, a second valve, an inverter and a third valve in series, a subtraction unit and a signal level analyzer are introduced into it, the second input of the first valve connected to the input interference level analyzer via the second valve, the first input of the third stem _to Pan combined with the input end of the phase analyzer sending the transmission and receiver input is discrete information, a trigger output connected to the second level analyzer inputs IQ of interference and the third valve, and also through the inverter - with the second input * of the second valve, the output of the interference level analyzer is connected to the second input of the subtraction unit, the output of counter 15 is connected to the second input of the signal level analyzer, the output of which is connected to the input of the level prediction unit signal.