SU1381597A1 - Rom (read-only-memory) - Google Patents

Abstract

The invention relates to computing and can be used in permanent storage devices. The aim of the invention is to increase the reliability of the persistent storage device. The goal is achieved by introducing a decoding unit and an inverting unit into the device, the information input and the correction inputs of the decoding unit are connected respectively to the output of the first storage device and the output of the second storage device, the inputs of the inverting unit are connected to the information inputs of the switchboard . 3 il.

Description

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with

The invention relates to computing and automation and can be used to create storage devices.

The purpose of the invention is to increase the reliability of a persistent storage device.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 — decoding unit and inversion unit; in fig. 3 - switch.

The device contains the first drive 1, the second drive 2, the first decoder 3, to input 4 of which the first part of the address code is connected, and the output is connected to the inputs of the first 1 and second 2 drives, decoding unit 5, the first input 6 of which is connected to the output of the first drive 1, the second input 7 with the output of the second accumulator 2, the first output 8 with the first input of the inverting unit 9, the second output 10 with the second input of the inverting unit 9. The output 11 of the inverting unit 9 is connected to the first input of the switch 12, the second input of which is connected to the output 13 of the second decoder 14. The second part of the address code is connected to the input 15 of the second decoder 14, and the output of the switch 12 is connected to the data bus 16.

Decoding unit 5 (FIG. 2) consists of K convolution schemes modulo two 17.1-17. L (K is determined from the relation

(m + fe + r),

where l | - the nearest integer is not less than X number;

g is the cell length of the second accumulator 2;

W - the length of the information part of the cell accumulator 1;

w-ffc is the cell length of accumulator 1, to the inputs of which the corresponding bits of the outputs of the first and second 2 drives are connected (in accordance with the Hamming code check matrix), decoder 18, the outputs of which are connected to the modulus two 17.1 - 17. Л, two-input adders modulo two 19.1 - 19.ш and two-input adders modulo two 20.1-20.l. The first inputs of the adders 19, 20 are connected to the same-named bits of the outputs of the first 1 and second 2 drives, respectively, and the decoder 18 outputs to the second inputs.

Block 9 inversion consists of adders modulo two 21.1-21.ot, the first inputs of which are connected to the same output of adders 19.1-19.t decoding unit 5, and the remaining inputs are outputs of adders 20.

Switch 12 (Fig. 3) consists of two-input elements And 22.1-22.sh, the first inputs of which are connected with the same-name bits 11.1 -. T of the output 11 of the inverting unit 9, and the second inputs - the corresponding bits 13.1 - 13. (t )

five

five

output 13 of the second decoder 14, and /, / - input elements OR 23.1-23./, the outputs of which are connected to the data bus 16.

The length g of the cell of accumulator 2 may vary within the limits. Connecting the outputs of the adders 20.1-20.g to the inputs of the summers 21.1-21.ш depends on the value of. For example, with block 5 it will contain only one type 20 adder, the output of which will be connected to the second inputs of all

10 adders 21.1-21.sh; in this case, all adders 21.1-21.sh will be two-input. The additional bits stored in the drive 2 are designed to mask the failed storage elements of the cell of the same name of the drive 1 by inverting the corresponding word bits to be entered into the drive when the device is manufactured. It is assumed that the location of the failures when programming the drive is known. Each additional bit is intended to invert a certain group of bits of the written word. These groups are chosen so that, with a given number of additional bits, they conceal as many faults as possible. If there is a failure when writing a word to a drive in some bit of a cell, then the group of bits of the source word, including the bit to be written to the failed cell storage element, under the condition of a discrepancy between the digit being written and the type of failure ("O or" 1), invert and the corresponding additional bit is written “1. Then, the word thus transformed, together with the additional bits, is encoded with a Hamming code and the result is stored in memory: the converted word and the control bits of the Hamming code are stored in drive 1, and invert bits are stored in drive 2. The listed operations are performed in the manufacture of ROM.

The information is read as follows.

According to the address code received at the input 4 (the first part of the address code) of the first decoder 3, the contents of the same-named drive cells I, 2 are selected and received

- in block 5 decoding. The read bit word is decoded and corrected (if an error occurs once). Corrections are made on modulo-two adders 19, 20, and only bits are corrected (correction of the check bits of the Hamming code is impractical, since they will not be used later). Correcting an error in some bit is equivalent to modulo two addition of the content of this bit with a unit. The location of the error is determined by the decoder 18 in accordance with the incoming to its inputs / (- the bit code of the syndrome, calculated

0

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0

0

convolution circuits 17.1-17 ./ (. Then the first tons of bits of the corrected word are fed to the first inputs of modulators two 21.1-2 tons of block 9 of inversion. In accordance with the values of g additional bits of inversion, the corresponding groups of t-bit are inverted Inverting is performed by incrementally modulo two bits of the group with the contents of the corresponding additional bit corresponding to this group. At the outputs of the adders 21.1-21 m, the restored original word is obtained.

Issuing information that you can use only one extra bit of inversion. In this case, the cells of accumulator 2 will contain one bit each, and all adders 21 will be two-input. In this case all 1,2,3-fold failures are masked. In the case of a storage cell containing Z () of failed storage elements, then the probability that all the failures will be masked is equal to

ten

(

The probability of masking 4x failures is 0.8; 5-fold failures - lt switch 12, controls the second de- 0.67; 6-fold - 0.57; 7-fold - 0.5. an encoder 14, to the input 15 of which enters

Claims (1)

the second part of the address code. In accordance with the formula of the invention With the code supplied to input 15, one of the / /-bit syllables / n-bit of the word enters the data bus 16. Commutator 12 is used in the case that the length of the cell I of the storage device equals the size of the data width 16. The expediency of introducing a switch is dictated by the need to reduce redundancy — the longer the length of the words being coded, the less redundancy. Therefore, it is desirable that the length of the words being processed should exceed the length of the output words on the IHHHV 16 data. 25 Permanent memory device containing the first power converter, inputs 20 of which are the first address inputs of the device, the first drive, the word buses of which are connected to the outputs of the first decoder, the second drive, the word buses of which are connected to the outputs of the first decryptor, the second decoder, the switch, the outputs of which are information outputs of the device, which otmirayus that, in order to increase the reliability of the device, a decoding unit was inserted into it, the information device allows to correct a one-time error not only in the information part of the read word , but in one of the additional inversion bits, i.e., the control covers both information and additional bits of the accumulator. The device allows masking of large-scale failures and correcting a one-time error; caused by failure. From the point of view of the simplicity of the device and reduction of redundancy, it is most advisable to use only one additional inversion bit. In this case, the cells of drive 2 will contain one bit each, and all adders 21 will be two-input. In this case all 1,2,3-fold failures are masked. In the case of a storage cell containing Z () of failed storage elements, then the probability that all the failures will be masked is equal to ( five Permanent memory device containing the first power converter, inputs 0, which are the first address inputs of the device, the first drive, the word buses of which are connected to the outputs of the first decoder, the second drive, the word buses of which are connected to the outputs of the first decryptor, the second decoder, the switch, the outputs of which are information outputs of the device, which otmirayus that, in order to increase the reliability of the device, a decoding unit has been entered into it, the information input of which is connected to the output of the first storage device, the correction inputs are connected to the output of th accumulator, inverting unit having inputs connected to respective outputs of the block decoding, and outputs connected to the inputs of the switch ing formational, sample discharge switch inputs connected to the outputs of the second decoder, the inputs of which are second addressable inputs. /// Jr // 5 / f.U rf.5 / f6 Itm-i 71. t Figg //; rt2 t / ft i / rr- z p. 21 fff.f 7Tm-f f /// 7g-L 7 / t