SU1379771A1 - Timer - Google Patents

Abstract

The invention relates to a technique of counting the current time using electronic devices. The purpose of the invention is to show the accuracy of timing. The device contains synchronization bus 1, triggers 2,12,13, generator 3, initial setup 4, elements AND 5-8, 16,17, OR 9 and 10, inverter 11, frequency divider 14, time counter 15, element OR-NOT 18, storage device 19, delay counter 20, switch 21, consisting of trigger 22, inverter 23, and elements 24 and 25. Introducing new elements and creating new connections between the elements of the device allows automatic full Correction of the reference rate when binding the readings of the device to the signals of the exact time. 5 il. 1C (/)

Description

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The purpose of: and 15–7––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

Il ffiir.l lead deia Functional with: heml ycTpoi iCTnaj on Lig, 2 - nremen-} 11. L2 diagrams of formion tactical packages; pa lig. - temporary diameters of 1-1mmmg, ilkrstrui1e vmg1s1Nedenia krrekpiii dark of the countdown at the start of the course of the device1 (stst; on fit; 4 - the same at retreat; figs 5 - and: -1plp 1: a-niU uMOCTii from the heading of arrivals; 1 nulls of the exact time.

The device contains a synchronization bus 1, a trigger 2, a generator, pin 4 of the initial installation, the first 5, BTOpoii 6, the third 7 and the fourth 8 And elements, the unbalanced 9 and the second 10 element -1 Я 1И, the inverter 11, the second 12 and retiy 1J triggers, divider 14 parts, time counter 1 .S, n 16 and | 1 | material 17 elements AND, elements OR-18, g memory device 19, delay counter 20 and switch 21 of trigger 22, inverter 23 and seventh 24 and BocjiMoro 25 elements AND,

OieTHtif t input of the frequency divider 14 is connected to the first output of the switch 21 of the delay, the second output of which is connected to the counting input of the counter 20 of the delay. The output of the generator 3 .connect with the first inputs of the elements And 5 and 6, and the output of the element And 5 is connected to the first input of the switch 21 of the delay, the second input of which is connected to the output of the element SH-II 1st, 1 1 of the synchronization 1 the installation input into unit T1) of the igger 2, the direct output of which is connected to the first input of the element Ш1И 9, the installation input to the unit of the trigger 12 and the second input of the And 6 element connected by the output with the first inputs of the And 7 and 8 elements. 111 ) and with the second input ele.menta ShII 9, the reset input of the counter 15 times audio input and write strobe 3lpominayu1chego device 19 by subtracting

79771

YUTION

ten

20

and the summation of the inputs of which are connected respectively to the outputs of d) lemme 16 and 17,

The output of the And 8 element is connected to the first inputs of the E: 16 and And 16 elements and Il lll 10, the output of which is connected to the summation of the Yutz input of the time counter 15, the second input is connected to the output of the delay counter 20 and the first input of the element element II 7 is connected to the first input of the element I) 7 and the subtractive input of the time counter 15, the zero output of which is connected to the reset input of the trigger 2 | Connected by its inverse output to the second input of the element 5, the discharge of the time counter 15 is connected to the second input of the element And 8, the counting inputs are three gage 12 and 13 and through the inverter 1I with the second input element And 7,

The second inputs of the elements 16 and 17 are connected to the output of the trigger 13, 25 connected by the input I) to the output of the trigger 12, the input of which is connected to the common device. The output of the IPI 9 element is connected to the third input of the delay switch 21 and the 30 sHphos splitter 14 frequency input, the overflow output of which is connected to the second input of the OR-AND element 18 and the input- ;, recording gate of the delay counter 20 connected to the cBoj.fMH data inputs of bits to the outputs of the storage device 19,

The device rsChbobota as follows.

When the device is turned on, a single impulse (from the outside or from the built-in driver) is applied to setup 4, which sets the time counter 15 to zero, and also (through the element OR 9) divider 14 and trigger 22. The same impulse to the entry strobe entry - 19, provides a record in it of the number M, the binary equivalent of which is permanently connected to the information inputs of the storage unit 19, the Time counter 15, set to the zero state, forms at its zero output a pulse arriving at K- trigger input 2; the latter also switches to a bullet state. The generator 3 generates a continuous sequence of reference pulses with the following frequency f, the Reference pulses through the elements And 5 and 24 post4G)

45

50

B5

n Е + М

ten

15

20

They are fed to the counting input of the frequency divider 1A, which counts them from zero, to the filling, when an overflow pulse is formed at its output.

The overflow pulse enters the C input of the counter 20 delay recording, so that the number stored in the memory 19 is rewritten into the bit one. The overflow pulse from the output of the frequency divider 14 is also inverted by the OR-NC 8 element and is fed to the counting trigger input 22. By the falling edge of the pulse trigger 22 is switched to one state. The potential of the inverse output of the trigger 22 locks the element And 24 and stops the operation of the divider frequency 14. In turn, the potential of the direct output of the trigger 22 permits the passage of the reference pulses through the inverter 23 and the AND element 25 to the counting input of the subtraction of the delay counter 20. At the rate of time of the reference pulses, the counter 20 delay 25 sequentially writes off the number written into it before going to the zero state, when a pulse is formed at its output. This pulse, through the SHSHE-18 element, by its falling edge, triggers the trigger 22 to the initial zero state. The alternate operation of the frequency divider 14 and the delay counter 20 is then cyclically repeated, and the contents of the memory 19 are entered into the delay counter 20 in each cycle, and the number of reference pulses , made upch each cycle (the volume of the clock package).

(one)

thirty

35

40

-Ü Fl ;,

. Where E is the capacitance of the frequency divider 14; MO is the average of the number of the stored memory 19;

t. - the current deviation of the number,., stored in memory 19, from the mean value of M. An impulse from the output of the delay counter 20, generated at the end of each clock packet, is fed through the OR 10 element to the counting input of the counter 15 and is used as a clock pulse when counting time. When the device is turned on, when there is still no reliable information about the current

50

(correction code), it is possible to correct (1-vat, the volume of the clock packet and, thus, the period of the following clock pulses (Fig. 2).

The exact time pulse received on 1 pin 1 synchronization switches trigger 2 to a single state. The zero potential of its inverse output stops the passage of reference pulses through the element And 5, the unit potential of the direct output of trigger 2 through the element OR 9 sets the frequency divider 14 and the trigger 22 to the zero state. The same potential allows the passage of reference pulses through element 6. The further course of the correction depends on the state of the counter 15 time.

If before the arrival of the exact time pulse, the time was read out ahead of time, then by the time the pulse arrives, the counter 15 is filled, goes into the zero state and has a certain number of pulses JN. Since the magnitude of the 4N reference error is much less than the number N of pulses x for the period T (and hence the capacity of the counter 15), the counter discharge 15 has a zero potential, which through the inverter li allows the passage of reference pulses (pulses) from the output element 6 through element 7 at the input of counter 15, which nlch1 / - accelerates the counting in the opposite direction - to the zero state

If the time count is well lagged, then by the arrival of the exact time pulse, the output of the most significant bit of the time counter has a single potential that permits the passage of the pulses from the output of the AND 6 element (incremental pulses) through the AND 8 element and the OR 10 element to the summing input of the counter 15 which in this case starts accelerated counting in the forward direction before filling and going to the zero state. Upon transition to the zero state, the counter 15 changes the potential at the output of the higher bit, which corresponds to the missing transfer unit for the subsequent time counters.

In both cases, the correction of the display of the frequency fj, of the reference pulses, to the memory is completed by the transition of the counter

as a correction code, the 15 is entered in the zero state, forming

its average value is MQ. The change in its zero pulse output, which is the number M o - ha; stored in the memory 19

rsh, entering the R-input of trigger 2,

0

five

0

five

0

five

0

,

0

(correction code), it is possible to correct (1-vat, the volume of the clock packet and, thus, the period of the following clock pulses (Fig. 2).

The exact time pulse received on 1 pin 1 of synchronization switches trigger 2 to a single state. The zero potential of its inverse output stops the passage of reference pulses through the element And 5, the unit potential of the direct output of trigger 2 through the element OR 9 sets the frequency divider 14 and the trigger 22 to the zero state. The same potential allows the passage of reference pulses through element 6. The further course of the correction depends on the state of the counter 15 time.

If before the arrival of the exact time pulse, the time was read out ahead of time, then by the time the pulse arrives, the counter 15 is filled, goes into the zero state and has a certain number of pulses JN. Since the magnitude of the 4N reference error is much less than the number N of pulses x for the period T (and hence the capacity of the counter 15), the counter discharge 15 has a zero potential, which through the inverter li allows the passage of reference pulses (pulses) from the output element 6 through element 7 at the input of counter 15, which nlch1 / - accelerates the counting in the opposite direction - to the zero state

If the time count is well lagged, then by the arrival of the exact time pulse, the output of the most significant bit of the time counter has a single potential that permits the passage of the pulses from the output of the AND 6 element (incremental pulses) through the AND 8 element and the OR 10 element to the summing input of the counter 15 which in this case starts accelerated counting in the forward direction before filling and going to the zero state. Upon transition to the zero state, the counter 15 changes the potential at the output of the higher bit, which corresponds to the missing transfer unit for the subsequent time counters.

In both cases, the correction of the readings is completed by switching over the counter.

and its zero pulse output, which

rsh, entering the R-input of trigger 2,

set n); 1nvaet trigger to the original (well,; ieRoe) state. The device is counting the time. It is infrequently that in both cases of correction of the switches, the transfer of counter 15 to the left state requires the number of pulses to be added to, equal to the deviation () of the actual (t counts of the number of clock pulses during the expired period N from the nominal1 of their number K:

 JTO is used to correct the reference stroke, the -ia period T between the two pulses themselves form an exact time; tsch: o T reference pulses. If and ((: current t period T) the value of the correction code M + n did not correspond to the current value “:; the frequency of the frequency and, as a result, the beat of the clock 11 pulses, then taking into account I 1)

 (+ G-1 about p j) (I-I + G) (2)

It is obvious that, in order to eliminate the error, it is necessary to set the code for the M d - -: tp correc- tion at which the wounded

G „T - (K +

+

(it is local

 -;.,) 11 pei itnuie (2.1 and (3)

gives

+ m

- 1 М „+ p. (I +

N.1, th

ten

3797716

and in order to implement the course correction, it is enough to complete the addition pulses (when correcting the readings to the counter 15, simultaneously feed the corresponding1 C1e C4e and n-ie inputs 19. In the proposed device, these pulses pass through AND 16 or 17 (FIG. .3 and 4 j.

The results of the course correction are satisfactory, provided that the norpei i is a count of 51; obtained in one interval T. In the event that previous pulses of the exact time were not received for one reason or another, the counting error is accumulated; Correction of the stroke in this case may lead to a sharp detuning of the device operation. To eliminate the effect of such an accumulation of readability, 1) -triggers 12 and 13 serve. The inputs of the cycles of these triggers are connected to the high-voltage output of counter 15, in which a positive voltage drop is formed in the middle of the interval T.

When this differential is passed, trigger 12 is always set to the zero position (since its input G has the potential of a logical zero constant), and trigger 13 assumes the state in which there was trigger 12 before the arrival of the differential, and retains this state before arrival the next differential from the output of counter 15,

20

25

(3) 30

35

(W. + M

given tg go that

Ln ff

g, Oh

t

+ t

E +

N

MO

JN, (M

Thus, in order to eliminate the LG1 reference error, the correction code needs to be changed by the amount it needs to be proportional to} 1st. Moreover, when advancing the course, the code of the CC should be increased, and if it is lagging behind, it should be reduced.

In order to prevent the implementation of the proposed arrangement, the constructive assumption

N,

one

- (M + sh.)

(five)

0

five

0

five

Trigger 12 can only be set to one state when a precise time pulse arrives at a high potential from the direct output of trigger 2. Thus, if the start of time interval T is received, the exact time pulse arrives, trigger one is in the unit state, the first half of this interval, trigger 13 - from the middle of this interval to the middle of the next. Therefore, when the next accurate time pulse arrives, the addition pulses pass through one of the elements AND 16 or 17 and the correction code is changed. If the exact time pulse is missed, the trigger 12 remains in the zero state, in the middle of the interval T the trigger I3 also passes to the zero state, therefore, the zero output potential of its direct output elements And 16 and 17 are closed. Therefore, only the readings of the counter 15 are corrected, and the correction code remains unchanged (Fig. 5).

Claims (1)

Invention Formula A timing device comprising a generator, a memory device, a time counter, a delay switch, a frequency divider and a delay counter, the counting input of the frequency divider is connected to the first output of the delay switch, the second output of which is connected to the counting input by a delay counter, characterized in that in order to measure the time accuracy by automatically correcting the counting rate while correlating the device readings to the time signals, the synchronization time, the starting bus settings, three triggers, six AND elements, two OR elements, an inverter and an N1NIE element, and the time counter is made in the form of a reversible counter, the storage device is made in the form of a reversible counter with pre-write buses and the delay counter is made in the form of a subtracting counter, the generator output is connected to the first inputs of the first and second elements AND, the output of the first element AND is connected to the first input of the delay switch, the second input of which is connected to the output of the element OR NOT, the sync bus is connected to the installation input to the first trigger, the direct output of which is connected to the first input of the first element OR, the installation input to 1 of the second trigger and the second input of the second element AND connected to the first input of the third and fourth elements) 1top I, 1in the initial installation is connected to the second the input of the first element OR, the reset input of the regregip counter and the input of the recording strobe of the device, the subtracting and summing inputs of which are connected respectively to the outputs of the fifth and honest elements I, the output of the fourth element M that is connected to the first inputs of the fifth AND gate and the second element №1I, vghod 1TSIM- coupled to an input of the time counter, and BTopoii  the input of the second element of the BOCH is connected to the output of the delay counter and the first input of the element ШИИ-НА, the output of the third element И is connected to the first input of the luecToro element AND and the subtractive 0 by the input of the time counter, zero zero of which is connected to the reset input of the first trigger connected by its inverse output with the second input of the first element AND, CTapriini The 5th bit of the time counter is connected to the second input of the fourth element I, the counting inputs of the second and third ariggers, and through the inverter to the second input of the third element I, the second Q inputs of the p and the element connected to the output of the third trigger, connected by its input G to the output of the second trigger, input D of which is connected to the common bus device}, the output of the first UTI element is connected to the third input of the gate switch and the reset input of the frequency divider whose overflow output is connected to the second input element 11CHI-NOT five and the entry gate of the recording of the delay counter connected by its data inputs bitwise to the outputs of the storage ycTpofiCTBa, Tongpo / th pinesh 3l. U5 Tl4nJl --- Jl-nJ L-Jl4n. I Al. GSG Healer / Tsasgpot / Al. silt and -NE 78 Ich Tpuz2ep 22. Al. ig5 Ci e / 77 L / f 10 I 3adep / K / L / Imlums movH. Trigger z . 75SpeMe (j State vshad g W /; sod ff (/ jf El.i7 Zopo / Ingestive l / C / 77pO (} c / 7f6o G9i. SOS / 770A / s o-f i rt h J-LTL I III phage.Z Pulse