SU1378062A1 - Voltage-to-frequency converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in systems for collecting and processing information for various purposes, automatic control and regulation systems. The invention allows to increase the speed. This is achieved by increasing the stability of the temporal position of the output pulses by introducing into the converter containing the operational amplifier 1, the comparator 4, the keys 3, 7, the source 8 of the discharge current, the D-flip-flop 5, the delay element. 1 hp ff, 3 ill.

Description

with

Nl

00

about o: IND

The invention relates to a pulse technique and is intended for use in systems for collecting and processing information of various kinds, automatic control and regulation systems.

The aim of the invention is to increase speed.

Fig. 2 shows the functional diagram of the converter; Fig. 2 is a functional block diagram of a bit control key; FIG. 3 shows timing diagrams of converter operation .-

The voltage to frequency converter (Fig. 1) contains an operational amplifier 1, a storage element.

2, made on the capacitor key

3, comparator 4, D-flip-flop 5, current limiting element 6, made on a resistor, switch 7, source

8 bit current, control bus 9, input bus I 10, clock bus P, bus 12 negative power source, reset bus 13, delay element 14, D-flip-flop 15 control block 16, output bus 17. Control box (fig.Z) contains elements NOT 18-20, elements OR-NOT 21-23, elements AND-NO 24 26,. RS-triggers 27 and 28.

Fig. 3a shows the reset signal; b - key control signal 3;

в - clock pulses; g - clock pulses at the output of the delay element; d - signal at the output of the operational amplifier 1; e, g, C - signals at the Q-output of D-flip-flop 5, Q-output of D-flip-flop 15 and output of block 16, respectively; and - the signal at the output of the operational amplifier 1 for the input signal, larger in magnitude than the signal in the diagram d corresponding to this input signal; K - signal at the Q-output of D-flip-flop 5; l - the signal at the Q-output of the D-flip-flop 15 m - the signal at the output of block 16.

The voltage to frequency converter operates as follows

An input signal is mounted on the input bus 10. When the signal O comes from the reset bus 13 (Fig. 3a), the S-inputs of the D-flip-flops 5 and 15 show signals 1 at their Q-outputs and the output of block 16 (Fig. 3, moment tp). At the same time from the control bus 9, a signal O is received (FIG. 3b), in effect

Key disconnecting key 3. The integrator built on operational amplifier 1, capacitor 2 and resistor 6 starts integrating the difference between the various and input currents during the period of the clock pulses and (fig. 3d, and interval tg-t,). In this case, the voltage at the output of the operational amplifier 1 becomes equal to

If - Ibx / 1

and

BblY MPHS

yu 15

20

25, 30

35

45

0

50

55

where IP is the value of the discharge current of source 8;

I century

 and j / R is the input current;

and g is the input voltage;

R is the resistance of the resistor 6. When the second clock pulse arrives, the signal O is set at the Q-output of D-flip-flop 5, at the output of block 16 (FIG. E, g, k, m, time t) and the Q-output of flip-flop 15 (FIG. .W, l, moment tj, t2 to + t3). The switch 7 is disconnected; the source 8 is disconnected from the operational amplifier 1, the voltage at the output of which begins to decrease (Fig. 3 h, i). When this voltage O is reached at the output of the comparator 3, a signal 1 appears at time tj. If the time interval between the output voltage of the operational amplifier 1 at the output of the operational amplifier 1 is 4 t c and the instant of the next clock pulse t is less than tt (o, + t

BEHIND

(FIG. 3d), then with the arrival of the clock pulse at the time (FIG. 3 B, pulse 4), the C-input of the trigger 5 remains at its Q-output O (FIG. 3e), and the signal does not appear I, as it would be in the case of t About (Fig. 3 d, e, dashed lines). The signal 1 at the output of the trigger 5 must be only at the moment of arrival of the next clock pulse (Fig. 3 v, pulse 5, time tti + J) to the C input of the trigger 5, i.e. there would be a pulse offset one clock interval to the right. In this case, the quantitative distribution of pulses at the Q output of flip-flop 5 varies over the Tpr transform intervals and T p, Vi. The signal 1 at the Q-output of the D-flip-flop 15 and the output of block 16 appears with the arrival of a clock pulse from the output element at the moment

14 to C-input D-flip-flop

Yes

15 at time t, j St -, + t, (FIG. 3, g, h). The element 14 delays the clock pulses received over the bus 11 at the time t With appearance 1 at the output of the block 16 the switch 7 is closed and the integration of the value 1 1 - Ij, begins. By the next clock

The IP pulse (Fig. 3g, pulse 5) the state of the D-flip-flop 15 and the output of the block 16 is changed (Fig. 3 g, g). At the output of block 16 a pulse of duration D (Fig. 3a) is formed, the moment of the occurrence of which falls within the interval of the transformation T "" j. This preserves the quantitative distribution of pulses in the code.

devices by intervals T

etc.

the process is repeated.

With a large signal at the input of the converter, if the time interval between the instant of crossing by the output voltage of the operational amplifier 1 of the level of operation of the comparator 4 (for example, when integrating the value of I p-Ig, time t

3 and) and the moment of occurrence of the nearest clock pulse t is less than t ,, then, with the arrival of the clock pulse at time ti (Fig. 3b, pulse 5), the output of D-flip-flop 5 is saved 1 (Fig. 3k), O does not appear, as it would have been at t4 O (FIG. 3 K, L, dashed lines). When this occurs, the pulses merge, and at the output of the trigger 5 a pulse of duration 21) is formed (FIG. 3k). As a result, the number of pulses (gaps) is reduced, which is formed at the output of the D-flip-flop 5 at intervals

TPR w in full range

N + I,

Transform Tpr 2 Ch.

In the case under consideration, with | 1 signal O at the output of D-flip-flop 15 (Fig. 4l and at the output of control unit 16 (Fig. 4 m)) appears at t -j t. With the appearance of signal O at output of block 16, the bit This key 7 and the integration of the value of I begins with the arrival of the next clock pulse (Fig. 3g, pulse 6) on Q-code of D-flip-flop 15 and the output of block 16 appears 1 (Fig. 3 lm), key 7 : zamyazhaet and integration begins

ranks

fefexWhen this, at the output of the D-flip-flop 15 a pulse of duration is formed, and at the output of the block

.

ten

15

20

25

thirty

35

40

45

 ) - 50

16 - a pulse of duration i - t (Fig. 3 l, m. As a result of the merging of the pulses at the output of the device does not occur and, accordingly, the number of pulses does not decrease in the intervals Trp, - and T.

If the time interval between the moment of crossing by the output voltage of the operational amplifier 1 of the comparator level (for example, tytu in FIG. 3 d, i) and the instant of the next clock pulse (fig.Sv, pulses 7 and 8, for moments t |, and respectively) is greater than t}, then with the arrival of the nearest clock pulse, a signal 1 appears at the Q-output of D-flip-flop 5 and output of block 16, and after time t, and at the output of D-flip-flop 15 (fig.Z e-z, q) and a pulse of duration is formed. The process then repeats. The input voltage of the converter is proportional to the average pulse frequency on the output bus 17.

Claims (2)

1. Voltage-to-frequency converter containing the first and second keys, a cumulative element made on a capacitor, a comparator, the first D-flip-flop, a current-limiting element made on a resistor, a source of discharge current, an operational amplifier whose inverting input is combined with the information input of the first key, the first capacitor plate, the first output of the resistor and is connected to the output of the second key; the non-inverting input is a common bus, the output is combined with the output of the first key and connected to the second one the capacitor key and the inverting input of a Comparator whose non-inverting input is a common bus and the comparator output is connected to the B input of the first D-flip-flop, the C input of which is the clock clock S-input — a reset bus, the information input of the second key through the source the discharge current is connected to the bus of the negative polarity source, the second output of the resistor is an input; the bus, the control input of the first key is a control bus, characterized in that the speed boost loop has a second D-flip-flop inserted, an expansion unit, a delay element whose input is a clock bus, and the output is connected to the C-input of the second B-flip-flop, whose input is connected to the comparator output , The S input is with a reset bus, and the direct output is with the first input of the control unit, the second input of which is connected to the direct output of the first D-flip-flop, and the output is connected to the reference input of the second key and is the output bus. 2. The converter according to claim 1, about t - l that is due to the fact that the block is integrated on three elms «- ta.x OR-NOT, three AND-NOT elements, two K3 triggers, three NOT elements, the input of the first of which is combined with the first inputs of the first elements OR-NOT and AND-NOT, and is the second input of the control unit, the output of the first element is NOT connected to the second inputs of the first elements OR-NOT and AND-HEj the third input of the first element AND-NO. connected to the inverse output of the first RS flip-flop, the R-input of which is combined with the first input of the second OR-NOT element and connected to the output of the third OR-NOT element, the first input of which is combined with the input of the second element NOT, the first input of the second element AND-NOT is The first input of the control unit, the second input of the third element OR-NOT is combined with the second input of the second element AND-NOT and connected to the output of the second element NOT, and the output of the second element AND-NOT is connected to the first input of the third element AND-NOT whose second input connected to you Odom first AND-NO, and output - with the S-input of the second RS-trigger, R-input which the third element is NOT connected to the output of the second element OR NOT, the direct output of the second RS flip-flop is the output of the control unit, the second input of the second element UTI-NOT combined with the B-input of the first RS-flip-flop and connected to the output of the first element OR NOT. 1 g T  and Tnaift tKV V