SU1378057A1 - A-d converter - Google Patents

Abstract

The invention relates to digital electrical engineering and can be used in adaptive systems for collecting and transmitting digital information. An analog-to-digital converter with an increased efficiency of adaptive analog-to-digital conversion by increasing the average adaptive sampling interval contains a reversible counter 4, the converter code is analog 5, the STI element 11, the first trigger 13, the time measurement unit 12, the second trigger 9, pulse generator 14, the first element is AND 1, register 16, the second 2 and the third 3 elements are AND, subtraction unit 6, subtractive counter 15, setting block 10, comparators 7.8. It follows from the principle of operation of the claimed converter that the ratio ut f is fulfilled for any moment of time, which allows restoring the source signal from memorized sequential samples by zero-degree polynomials with an error not exceeding the value. The sampling interval is determined by the time during which the increment of the signal to be converted will reach 2. 2 or less. (L

Description

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The invention relates to digital electrical engineering and can be used in adaptive systems for collecting and transmitting digital information.

The purpose of the invention is to exclude from the exaggeration of output information

Fig. 1 shows a block diagram of a converter} in Fig. 2, a diagram explaining its operation;

The analog-to-digital converter contains the first 1, second 2 and third 3 elements AND, the reversible counter 4, the converter 5 code — analog, block 6 subtraction, first 7 and second 8 comparators, trigger 9, block 10 of the setpoint, element OR 1) , block 12 of time measurement, trigger, 3, generator of 14 pulses, subtracting counter 15, register 16.

The Converter operates as follows.

In the initial state, the number 2n-1 is written in the subtracting counter 15. Let at time t, - (FIG. 2) the difference between the converted U and the approximating Ug signals reached the aperture value ElU - the output voltage of the converter 5 code is analog), and u (t U) f (t, .- Ua ( t, -),, where a (t) is the output voltage of subtraction unit 6. Comparators 7 and 8 operate respectively under the conditions / i (t) - and i (t) /)) 6. Consequently, at time t, the second comparator 8 is triggered and the pulse at its output sets the trigger 9 to the zero state. This same pulse, passing through the element OR 1 1. Sets the trigger 13 to one state. Starting from this moment, the pulses from the generator output 14 of the pulses arrive through elements II and 3 to the summing input of the reversible counter 4, increasing its content. From the moment the trigger 13 is set to the single state, the -1 pulses of the generator 14 also arrive at the counting input of the detracting counter 15, reducing its contents. which sets the second trigger 13 to the zero state, and also leads to the entry in the counter of the 15 digit of the number 2m;

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from the block 10 of the setpoint, and to write to the register 16 the contents of the reversible counter 4 (where f is the period of the pulses from the generator

14; and .-, where q is the signal gain

and when changing the contents of the reversible counter 4 by one). FIG. 2 shows the case for m 4. Thus, at time tj + 2i; output voltage Ucr converter 5 code - analogue is

U "(t ,. + 2m U, (t;) + 2mq U (t,) - f + 2f U, (t,) + f,

its digital equivalent is recorded in register 16. A time measurement unit 12 measures a time interval dt; tj - t between the moments of occurrence of pulses at the output of the element OR II. The numerical value of X; and t are the coordinates of a significant reference of the input signal and are the result of an adaptive analog-digital conversion. I

If at time t .- (Fig. 2) (t. J) -f, the first comparator 7 is triggered. At this, the trigger 9 is set to one state and the pulses from the generator 14 through the elements 1 and 2 are fed to the subtracting input reversible counter 4. The rest of the operation of the device is similar to that described previously. At the same time, U (, j (tj + 2ш1) U; (tj) - E. From the principle of the claimed converter, it follows that for any moment in time the relation Iui t I B is fulfilled, which allows restoring the original signal from the memorized zero degree polynomials with an error not exceeding the value.

Claims (1)

Invention Formula An analog-to-digital converter containing a subtractor, the first input of which is an input bus, the second input is connected to the output of the code-analog converter, and the output is connected to the first inputs of the first and second comparators, the second inputs of which are tires of threshold voltages opposite to fields converters, the analogue code converter inputs are connected to the corresponding the outputs of a reversible counter, the control inputs of which are connected respectively to the outputs of the first and second elements AND, the first inputs of which are combined and connected to the output of the third element AND, the first input of which is connected to the output of the pulse generator, with, Q to eliminate redundancy of output, the first and second triggers, aneMeHt, are introduced into it. OR, the setpoint block, the subtracting counter, the register and the time measurement block, tc whose output is the bus of the time interval code, the input is combined with the first input of the first trigger and connected via the OR element to the outputs of the first and second comparators Respectively, the outputs of which are connected to the corresponding inputs of the second trigger, whose outputs are connected to the second inputs of the first and second elements And, respectively, the second input of the third element And connected to the output of the first trigger, the second input of which is combined with the input of the code reading of the detracting counter and register ft to the output of the subtracting counter, the information inputs of which are connected to the outputs of the setpoint unit, respectively, and the information inputs of the register, to the outputs of the reversible counter, respectively, output S are the output bus, the output of the third element I is connected to the counting input of the subtracting counter. Phage. 2